Product Overview
Product Category: | Embedded - Microprocessors |
Kynix Part #: | KY32-XPC8260ZUIHBC |
Manufacturer Part#: | XPC8260ZUIHBC |
Manufacturer | Freescale Semiconductor - NXP |
Description: | IC MPU MPC82XX 200MHZ 408TBGA |
Package: | 480-LBGA |
Datasheet: | |
Stock: | Yes |
Quantity: | 516 PCS |
XPC8260ZUIHBC Images are for reference only:
Product Specifications
Categories | Integrated Circuits (ICs) Embedded - Microprocessors |
Manufacturer | NXP USA Inc. |
Series | MPC82xx |
Packaging | Tray |
Part Status | Obsolete |
Core Processor | PowerPC G2 |
Number of Cores/Bus Width | 1 Core, 32-Bit |
Speed | 200MHz |
Co-Processors/DSP | Communications; RISC CPM |
RAM Controllers | DRAM, SDRAM |
Graphics Acceleration | No |
Display & Interface Controllers | - |
Ethernet | 10/100Mbps (3) |
SATA | - |
USB | - |
Voltage - I/O | 3.3V |
Operating Temperature | 0°C ~ 105°C (TA) |
Security Features | - |
Package / Case | 480-LBGA Exposed Pad |
Supplier Device Package | 480-TBGA (37.5x37.5) |
Additional Interfaces | I²C, SCC, SMC, SPI, UART, USART |
Base Part Number | PC8260 |
Mfr Package Description | 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
Status | Discontinued |
Address Bus Width | 32.0 |
Bit Size | 32 |
Boundary Scan | YES |
Clock Frequency-Max | 66.66 MHz |
External Data Bus Width | 64.0 |
Format | FLOATING POINT |
Integrated Cache | YES |
JESD-30 Code | S-PBGA-B480 |
JESD-609 Code | e0 |
Low Power Mode | NO |
Moisture Sensitivity Level | 3 |
Number of Terminals | 480 |
Operating Temperature-Min | 0.0 Cel |
Operating Temperature-Max | 70.0 Cel |
Package Body Material | PLASTIC/EPOXY |
Package Code | LBGA |
Package Shape | SQUARE |
Package Style | GRID ARRAY, LOW PROFILE |
Peak Reflow Temperature (Cel) | 220 |
Qualification Status | Not Qualified |
Seated Height-Max | 1.65 mm |
Speed | 200.0 MHz |
Supply Voltage-Nom | 1.8 V |
Supply Voltage-Min | 1.7 V |
Supply Voltage-Max | 1.9 V |
Surface Mount | YES |
Technology | CMOS |
Temperature Grade | COMMERCIAL |
Terminal Finish | TIN LEAD |
Terminal Form | BALL |
Terminal Pitch | 1.27 mm |
Terminal Position | BOTTOM |
Time@Peak Reflow Temperature-Max (s) | 30 |
Length | 37.5 mm |
Width | 37.5 mm |
XPC8260ZUIHBC Datasheet PDF Download:
Block Diagram
Fig 1. MPC8260 Block Diagram
Pin Assignments
Fig 2. Pinout of the 480 TBGA Package as Viewed from the Top Surface
Description
There is no relevant information available for this part yet.
Features
The major features of the MPC8260 are as follows:
• Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the MPC8255)
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
• Separate power supply for internal logic and for I/O
• Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
• 64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
• 32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
• System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE Std 1149.1™ JTAG test access port
• Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
• CPU core can be disabled and the device can be used in slave mode to an external core
• Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols
— Interfaces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers (two on the MPC8255) supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE Std 802.3™ CDMA/CS interface through media independent interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I2 C) controller (identical to the MPC860 I2 C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to eight TDM interfaces (4 on the MPC8255)
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
Other data sheets within the file:
Datasheets | |
MPC8260 PowerQUICC II Family | |
Development Tool Selector | |
PCN Design/Specification | |
EOL 01/Apr/2016 |