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Apr 16 2019

XC6SLX45-2FGG484I Datasheet PDF –FPGA Spartan-6 LX Family 43661 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate   Array)

Kynix Part #:

KY32-XC6SLX45-2FGG484I

Manufacturer Part#:

XC6SLX45-2FGG484I

Manufacturer

XILINX

Description:

IC FPGA 316 I/O 484FBGA

Package:

BGA

Datasheet:

XC6SLX45-2FGG484I Datasheet

Stock:

Yes

Quantity:

1145 PCS

XC6SLX45-2FGG484I Images are for reference only:

XC6SLX45-2FGG484I

 

Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

XILINX

Status      

Active

Series

Spartan®-6 LX

REACH Compliant

Yes

EU RoHS Compliant

Yes

Speed Grade

2

ECCN

3A991.d

HTSN

PARTS...

SCHEDULE B

PARTS...

Clock Frequency-Max

667.0 MHz

Combinatorial Delay of a CLB-Max

0.26 ns

JESD-30 Code

S-PBGA-B484

JESD-609 Code

e1

Lead Finish

Tin/Silver/Copper

Maximum Operating Supply Voltage

1.26 V

Minimum Operating Supply Voltage

1.14 V

Moisture Sensitivity Level

3

Number of LABs/CLBs

3411.0

Number of Inputs

316.0

Number of Logic Elements/ Cells

43661.0

Number of Outputs

316.0

Number of Terminals

484

Number of Registers

54,576

Number of I/O

316

Organization

3411 CLBS

Operating Temperature-Min

-40.0 °C

Operating Temperature-Max

85.0 °C

Package-Case

484-BBGA

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Equivalence Code

BGA484,22X22,40

Package Shape

SQUARE

Package Style

GRID ARRAY

Peak Reflow Temperature

250 °C

Power Supplies

1.2,2.5/3.3

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Pin Count

484

Seated Height-Max

2.6 mm

Sub Category

Field Programmable Gate Arrays

Screening Level

Industrial

Supply Voltage-Nom

1.2 V

Supply Voltage-Min

1.14 V

Supply Voltage-Max

1.26 V

Surface Mount

Yes

Technology

CMOS

Temperature Grade

INDUSTRIAL

Terminal Finish

Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

Terminal Form

BALL

Terminal Pitch

1.0 mm

Terminal Position

BOTTOM

Total RAM Bits

2138112

Typical Operating Supply Voltage

1.2000 V

Length

23.0 mm

Width

23.0 mm

In System Programmability

No

Re-programmability Support

1

XC6SLX150-3FGG676C Datasheet PDF Download:

XC6SLX45-2FGG484I Datasheet PDF

Spartan-6 FPGA Feature Summary

Table 1 Spartan-6 FPGA Feature Summary by Device

Table 1: Spartan-6 FPGA Feature Summary by Device

 Spartan-6 FPGA Device-Package Combinations and Available I/Os

Table 2 Spartan-6 Device-Package Combinations and Maximum Available I,Os

Table 2: Spartan-6 Device-Package Combinations and Maximum Available I/Os

Spartan-6 FPGA Ordering Information

Table 3 shows the speed and temperature grades available in the different Spartan-6 devices. Some devices might not be available in every speed and temperature grade.

Table 3  Speed Grade and Temperature Ranges

Table 3: Speed Grade and Temperature Ranges

The Spartan-6 FPGA ordering information shown in Figure 1 applies to all packages, including Pb-Free. Refer to the Package Marking section of UG385, Spartan-6 FPGA Packaging and Pinouts for a more detailed explanation of the device markings.

 Figure 1 Spartan-6 FPGA Ordering Information

Fig 1. Spartan-6 FPGA Ordering Information

Description

The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins.

Features

• Spartan-6 Family:

Spartan-6 LX FPGA: Logic optimized

Spartan-6 LXT FPGA: High-speed serial connectivity

• Designed for low cost

Multiple efficient integrated blocks

Optimized selection of I/O standards

Staggered pads

High-volume plastic wire-bonded packages

• Low static and dynamic power

45 nm process optimized for cost and low power

Hibernate power-down mode for zero power

Suspend mode maintains state and configuration with multi-pin wake-up, control

enhancement

• Lower-power 1.0V core voltage (LX FPGAs, -1L only)

High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -3N speed grades)

• Multi-voltage, multi-standard SelectIO™ interface banks

Up to 1,080 Mb/s data transfer rate per differential I/O

Selectable output drive, up to 24 mA per pin

3.3V to 1.2V I/O standards and protocols

Low-cost HSTL and SSTL memory interfaces

Hot swap compliance

Adjustable I/O slew rates to improve signal integrity

• High-speed GTP serial transceivers in the LXT FPGAs

Up to 3.2 Gb/s

High-speed interfaces including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI

Integrated Endpoint block for PCI Express designs (LXT)

• Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.

• Efficient DSP48A1 slices

High-performance arithmetic and signal processing

Fast 18 x 18 multiplier and 48-bit accumulator

Pipelining and cascading capability

Pre-adder to assist filter applications

• Integrated Memory Controller blocks

DDR, DDR2, DDR3, and LPDDR support

Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth)

Multi-port bus structure with independent FIFO to reduce design timing issues

• Abundant logic resources with increased logic capacity

Optional shift register or distributed RAM support

Efficient 6-input LUTs improve performance and minimize power

LUT with dual flip-flops for pipeline centric applications

• Block RAM with a wide range of granularity

Fast block RAM with byte write enable

18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs

• Clock Management Tile (CMT) for enhanced performance

Low noise, flexible clocking

Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion

Phase-Locked Loops (PLLs) for low-jitter clocking

Frequency synthesis with simultaneous multiplication, division, and phase shifting

Sixteen low-skew global clock networks

• Simplified configuration, supports low-cost standards

2-pin auto-detect configuration

Broad third-party SPI (up to x4) and NOR flash support

Feature rich Xilinx Platform Flash with JTAG

MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection

• Enhanced security for design protection

Unique Device DNA identifier for design authentication

AES bitstream encryption in the larger devices

• Faster embedded processing with enhanced, low cost, MicroBlaze™ soft processor

• Industry-leading IP and reference designs

Other data sheets within the file:

Datasheet

Spartan-6 FPGA Datasheet

Spartan-6 FPGA Datasheet

Spartan-6   Family Overview

Spartan-6 Family Overview

PCN Design/Specification

FG(G)   and BG(G) Wire Bond 25/Jan/2013

FG(G) and BG(G) Wire Bond 25Jan2013


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