Product Overview
Product Category: | Embedded - FPGAs (Field Programmable Gate Array) |
Kynix Part #: | KY32-XC5VLX85-1FF676I |
Manufacturer Part#: | XC5VLX85-1FF676I |
Manufacturer | Xilinx Inc. |
Description: | IC FPGA 440 I/O 676FCBGA |
Package: | 676-BBGA, FCBGA |
Datasheet: | |
Stock: | Yes |
Quantity: | 141 PCS |
XC5VLX85-1FF676I Images are for reference only:
Product Specifications
Product Category | Embedded - FPGAs (Field Programmable Gate Array) |
Manufacturer | Xilinx Inc. |
Status | Active |
Series | Virtex®-5 LX |
Package/Case | 676-BBGA, FCBGA |
Clock Frequency-Max | 1098.0 MHz |
Distributed RAM | 840 kbit |
Device Logic Cells | 82944 |
Device Logic Units | 82944 |
Embedded Block RAM - EBR | 3456 kbit |
In System Programmability | Yes |
JESD-30 Code | S-PBGA-B676 |
JESD-609 Code | e0 |
Lead Finish | Tin/Lead |
Mounting-Type | Surface Mount |
Mounting Style | SMD/SMT |
Moisture Sensitivity Level | 4 |
Maximum Operating Frequency | 550 MHz |
Number of I/O | 440 |
Number of Pins | 676 |
Number of LABs/CLBs | 6480 |
Number of Inputs | 440.0 |
Number of Logic Cells | 82944.0 |
Number of Outputs | 440.0 |
Number of Terminals | 676 |
Organization | 6480 CLBS |
Operating Temperature-Min | -40.0°C |
Operating Temperature-Max | 100.0°C |
Pin Count | 676 |
Power Supplies | 1,2.5 |
Product Type | FPGA - Field Programmable Gate Array |
Package Body Material | PLASTIC/EPOXY |
Package Code | BGA |
Package Equivalence Code | BGA676,26X26,40 |
Package Shape | SQUARE |
Package Style | GRID ARRAY |
Peak Reflow Temperature | 225°C |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
Process Technology | 90 nm |
RAM Bits | 3,538,944 Bit |
RAM Size | 432 kB |
REACH Compliant | Yes |
Seated Height-Max | 3.0 mm |
Speed Grade | 1 |
Sub Category | Field Programmable Gate Arrays |
Screening Level | Industrial |
Supply Voltage-Nom | 1.0 V |
Supply Voltage-Min | 0.95 V |
Supply Voltage-Max | 1.05 V |
Surface Mount | Yes |
Supplier Device Package | 676-FCBGA (27x27) |
Technology | CMOS |
Tradename | Virtex |
Terminal Finish | Tin/Lead (Sn63Pb37) |
Terminal Form | BALL |
Terminal Pitch | 1.0 mm |
Terminal Position | BOTTOM |
Total RAM Bits | 3538944 |
Time@Peak Reflow Temperature-Max | 30 s |
Length | 27.0 mm |
Width | 27.0 mm |
XC5VLX85-1FF676I Datasheet PDF Download:
Description
Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), themost choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, secondgeneration 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms includeadvanced high-speed serial connectivity and link/transaction layer capability.
Features
• Five platforms LX, LXT, SXT, TXT, and FXT
− Virtex-5 LX: High-performance general logic applications
− Virtex-5 LXT: High-performance logic with advanced serial connectivity
− Virtex-5 SXT: High-performance signal processing applications with advanced serial connectivity
− Virtex-5 TXT: High-performance systems with double density advanced serial connectivity
− Virtex-5 FXT: High-performance embedded systems with advanced serial connectivity
• Cross-platform compatibility
− LXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulators
• Most advanced, high-performance, optimal-utilization, FPGA fabric
− Real 6-input look-up table (LUT) technology
− Dual 5-LUT option
− Improved reduced-hop routing
− 64-bit distributed RAM option
− SRL32/Dual SRL16 option
• Powerful clock management tile (CMT) clocking
− Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
− PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
• 36-Kbit block RAM/FIFOs
− True dual-port RAM blocks
− Enhanced optional programmable FIFO logic
− Programmable
- True dual-port widths up to x36
- Simple dual-port widths up to x72
− Built-in optional error-correction circuitry
− Optionally program each block as two independent 18-Kbit blocks
• High-performance parallel SelectIO technology
− 1.2 to 3.3V I/O Operation
− Source-synchronous interfacing using ChipSync™ technology
− Digitally-controlled impedance (DCI) active termination
− Flexible fine-grained I/O banking
− High-speed memory interface support
• Advanced DSP48E slices
− 25 x 18, two’s complement, multiplication
− Optional adder, subtracter, and accumulator
− Optional pipelining
− Optional bitwise logical functionality
− Dedicated cascade connections
• Flexible configuration options
− SPI and Parallel FLASH interface
− Multi-bitstream support with dedicated fallback reconfiguration logic
− Auto bus width detection capability
• System Monitoring capability on all devices
− On-chip/Off-chip thermal monitoring
− On-chip/Off-chip power supply monitoring
− JTAG access to all monitored quantities
• Integrated Endpoint blocks for PCI Express Designs
− LXT, SXT, TXT, and FXT Platforms
− Compliant with the PCI Express Base Specification 1.1
− x1, x4, or x8 lane support per block
− Works in conjunction with RocketIO™ transceivers
• Tri-mode 10/100/1000 Mb/s Ethernet MACs
− LXT, SXT, TXT, and FXT Platforms
− RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) options
• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
− LXT and SXT Platforms
• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
− TXT and FXT Platforms
• PowerPC 440 Microprocessors
− FXT Platform only
− RISC architecture
− 7-stage pipeline
− 32-Kbyte instruction and data caches included
− Optimized processor interface structure (crossbar)
• 65-nm copper CMOS process technology
• 1.0V core voltage
• High signal-integrity flip-chip packaging available in standard or Pb-free package options
Other data sheets within the file:
Datasheet | |
Virtex-5 Family Overview | ![]() |
Virtex-5 FPGA Datasheet | ![]() |
Virtex-5 FPGA User Guide | ![]() |
PCN Design/Specification | |
Substrate BallPad Metal Change 8/Feb/2016 | ![]() |