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Jan 9 2020

XC4010E-3PC84I Datasheet PDF – IC FPGA 61 I/O 84PLCC Xilinx Inc.

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-XC4010E-3PC84I

Manufacturer Part#:

XC4010E-3PC84I

Manufacturer

Xilinx Inc.

Description:

IC FPGA 61 I/O 84PLCC

Package:

84-LCC (J-Lead)

Datasheet:

XC4010E-3PC84I Datasheet

Stock:

Yes

Quantity:

895 PCS


XC4010E-3PC84I Images are for reference only:

XC4010E-3PC84I 


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Xilinx Inc.

Series

XC4000E/X

Clock Frequency-Max

125.0 MHz

Combinatorial Delay of a CLB-Max

2.0 ns

Distributed RAM

12800 bit

JESD-30 Code

S-PQCC-J84

JESD-609 Code

e0

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

3

Maximum Operating Frequency

150 MHz

Number of I/Os

61

Number of CLBs

400.0

Number of Gates

10000

Number of Inputs

160.0

Number of Logic Cells

400.0

Number of Outputs

160.0

Number of Terminals

84

Number of LABs/CLBs

400

Number of Logic Elements/Cells

950

Number of Equivalent Gates

7000.0

Organization

400 CLBS, 7000 GATES

Operating Temperature-Min

-40.0°C

Operating Temperature-Max

100.0°C

Package / Case

84-LCC (J-Lead)

Package Body Material

PLASTIC/EPOXY

Package Code

QCCJ

Package Equivalence Code

LDCC84,1.2SQ

Package Shape

SQUARE

Package Style

CHIP CARRIER

Peak Reflow Temperature

225°C

Power Supplies

5

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Product Type

FPGA - Field Programmable Gate Array

RAM Size

1.6 kB

Seated Height-Max

5.08 mm

Sub Category

Field Programmable Gate Arrays

Supply Voltage-Nom

5.0 V

Supply Voltage-Min

4.5 V

Supply Voltage-Max

5.5 V

Surface Mount

Yes

Supplier Device Package

84-PLCC (29.31x29.31)

Technology

CMOS

Total RAM Bits

12800

Terminal Finish

Tin/Lead (Sn85Pb15)

Terminal Form

J BEND

Terminal Pitch

1.27 mm

Terminal Position

QUAD

Time@Peak Reflow Temperature-Max

30 s

Length

29.3116 mm

Width

29.3116 mm

Voltage-Supply

4.5V ~ 5.5V

RoHS Compliant

Yes

Lead Free Status

Lead Free


XC4010E-3PC84I Datasheet PDF Download:

XC4010E-3PC84I Datasheet PDF

Block Diagram

Figure 1.Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown) 

Figure 1.Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)

Figure 2.Simplified Block Diagram of XC4000E IOB

Figure 2.Simplified Block Diagram of XC4000E IOB

Figure 3.Simplified Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)

Figure 3.Simplified Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)

Description

XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array.

The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated

software to achieve fully automated implementation of complex, high-density, high-performance designs.

Features

• System featured Field-Programmable Gate Arrays

- SelectRAMTM memory: on-chip ultra-fast RAM with

- synchronous write option

- dual-port RAM option

- Fully PCI compliant (speed grades -2 and faster)

- Abundant flip-flops

- Flexible function generators

- Dedicated high-speed carry logic

- Wide edge decoders on each edge

- Hierarchy of interconnect lines

- Internal 3-state bus capability

- Eight global low-skew clock or signal distribution networks

• System Performance beyond 80 MHz

• Flexible Array Architecture

• Low Power Segmented Routing Architecture

• Systems-Oriented Features

- IEEE 1149.1-compatible boundary scan logic support

- Individually programmable output slew rate

- Programmable input pull-up or pull-down resistors

- 12 mA sink current per XC4000E output

• Configured by Loading Binary File

- Unlimited re-programmability

• Read Back Capability

- Program verification

- Internal node observability

• Backward Compatible with XC4000 Devices

• Development System runs on most common computer platforms

- Interfaces to popular design environments

- Fully automatic mapping, placement and routing

- Interactive design editor for design optimization

• Low-Voltage Devices Function at 3.0 - 3.6 Volts

• XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices

• High Performance — 3.3 V XC4000XL

• High Capacity — Over 180,000 Usable Gates

• 5 V tolerant I/Os on XC4000XL

• 0.35 µm SRAM process for XC4000XL

• Additional Routing Over XC4000E

- almost twice the routing capacity for high-density designs

• Buffered Interconnect for Maximum Speed Blocks

• Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility

• 12 mA Sink Current Per XC4000X Output

• Flexible New High-Speed Clock Network

- Eight additional Early Buffers for shorter clock delays

- Virtually unlimited number of clock signals

• Optional Multiplexer or 2-input Function Generator on Device Outputs

• Four Additional Address Bits in Master Parallel Configuration Mode


Other data sheets within the file:

Datasheet

XC4010E-3PC84I Datasheet

XC4010E-3PC84I Datasheet

PCN Obsolescence/ EOL

XC4000E,XLA,1700L,E,EL,17S00,XL Families 28/Jul/2010

XC4000E,XLA,1700L,E,EL,17S00,XL Families 28/Jul/2010


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