S29GL064M90TFIR40 Datasheet PDF – NOR Flash Parallel 3V/3.3V 64M-bit 8M x 8/4M x 16 90ns 48-Pin TSOP Tray

Product Overview

S29GL064M90TFIR40 Images are for reference only:

Product Specifications

S29GL064M90TFIR40 Datasheet PDF Download:

Block Diagram

Fig. 1 Device Block Diagram

Connection Diagrams

Notes:

1. Pin 13 is NC on S29GL032M.

2. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is VIO on S29GL064M (models R6, R7).

Fig. 2 40-Pin Standard TSOP and 48-Pin Standard TSOP

For S29GL064M (model R0) only

Fig. 3 48-Pin Standard TSOP

Fig. 4 56-Pin Standard TSOP

Notes:

1. Pin 1 is NC on S29GL128M, 29GL064M, and S29GL032M.

2. Pin 2 is NC on S29GL064M, and S29GL032M.

3. Pin 15 is NC on S29GL032M.

Fig. 5 64-ball Fortified BGA

Notes:

1. Ball C5 is NC on S29GL032M.

2. Ball B8 is NC on S29GL064M and S29GL032M.

3. Ball C8 is NC on S29GL128M, S29GL064M and S29GL032M.

4. Ball D8 and Ball F1 are NC on S29GL064M (models R3, R4) and S29GL032M (models R3, R4, R5, R6).

5. Ball F7 is NC on S29GL064M (model R5).

Fig. 6 63-Ball Fine-Pitch BGA

Note: Ball H7 is VIO on S29GL064M (model R5).

Pin Description

Description

The S29GL256/128/064/032M family of devices are 3.0 V single power Flash memory manufactured using 0.23 µm MirrorBit technology. The S29GL256M is a 256†Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128M is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The S29GL064M is a 64 Mbit, organized as 4,194,304 words or 8,388,608 bytes.

The S29GL032M is a 32 Mbit, organized as 2,097,152 words or 4,194,304 bytes. Depending on the model number, the devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The devices can be programmed either in the host system or in standard EPROM programmers.

Access times as fast as 90 ns (S29GL128M, S29GL064M, S29GL032M) or 100 ns (S29GL256M) are available. Note that each access time has a specific operating voltage range (VCC) as specified in

Product Selector Guide and the Ordering Information sections starting on page 16. Package offerings include 40-pin TSOP, 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA, 63-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.

Device programming and erasure are initiated through command sequences. Once a program or erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four.

Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both  program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment.

The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The

Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry.

A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses are stable for a specified period of time.

The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the

WP#/ACC pin or WP# pin, depending on model number. The protected sector is still protected even during accelerated programming.

The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur.

Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

Distinctive Characteristics

Architectural Advantages

• Single power supply operation

— 3 volt read, erase, and program operations

• Manufactured on 0.23 µm MirrorBit process technology

• Secured Silicon Sector region

— 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence

— May be programmed and locked at the factory or by the customer

• Flexible sector architecture

— 256 Mb: 512 32-Kword (64 Kbyte) sectors

— 128 Mb: 256 32-Kword (64 Kbyte) sectors

— 64 Mb (uniform sector models): 128 32-Kword (64-Kbyte) sectors or 128 32 Kword sectors

— 64 Mb (boot sector models): 127 32-Kword (64-Kbyte) sectors + 8 4Kword (8Kbyte) boot sectors

— 32 Mb (uniform sector models): 64 32-Kword (64-Kbyte) sectors of 64 32-Kword sectors

— 32 Mb (boot sector models): 63 32-Kword (64 Kbyte) sectors + 8 4-Kword (8-Kbyte) boot sectors

• Compatibility with JEDEC standards

— Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write protection

• 100,000 erase cycles typical per sector

• 20-year data retention typical

Performance Characteristics

• High performance

— 90 ns access time (128 Mb, 64 Mb, 32 Mb), 100 ns access time (256 Mb)

— 4-word/8-byte page read buffer

— 25 ns page read times (128 Mb, 64 Mb, 32 Mb)

— 30 ns page read times (256 Mb)

— 16-word/32-byte write buffer

— 16-word/32-byte write buffer reduces overall programming time for multiple-word updates

• Low power consumption (typical values at 3.0 V,5 MHz)

— 18 mA typical active read current (64 Mb, 32 Mb)

— 25 mA typical active read current (256 Mb, 128 Mb)

— 50 mA typical erase/program current

— 1 µA typical standby mode current

• Package options

— 40-pin TSOP

— 48-pin TSOP

— 56-pin TSOP

— 64-ball Fortified BGA

— 48-ball fine-pitch BGA

— 63-ball fine-pitch BGA

Software & Hardware Features

• Software features

— Program Suspend & Resume: read other sectors before programming operation is completed

— Erase Suspend & Resume: read/program other sectors before an erase operation is completed

— Data# polling & toggle bits provide status

— CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices

— Unlock Bypass Program command reduces overall multiple-word programming time

• Hardware features

— Sector Group Protection: hardware-level method of preventing write operations within a sector group

— Temporary Sector Unprotect: VID-level method of charging code in locked sectors

— WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings on uniform sector models

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) detects program or erase cycle completion

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