**Catalog**

I | Overview | |

II | LS Wavelet Transform Theory | |

III | Realization of FPGA and Lifting Core | FPGA and Refactoring Features |

The Realization of Lifting Wavelet Transform Kernel | ||

IV | Logical Synthesis Result | |

V | Conclusion |

**Overview**

Wavelet transform based on lifting scheme can realize many kinds of wavelet transform with FPGA programmable feature. LS: extension Scheme. LS is a wavelet transform method proposed by Sweldens et al in recent years. With its framework structure, DWT can be effectively calculated. For longer filters, the number of LS operations is reduced by nearly half compared with the filter bank operation, which is more suitable for hardware implementation. According to the framework structure of improved wavelet transform, we can construct different wavelet transform cores by using the feature that FPGA can be reconstructed completely, so as to meet the requirements of different applications. The bottom-up design method is adopted in the structural design, and each promotion step is represented by some programmable parameters, which ensures that each step can be reconstructed. These parameters include the number of bits used to represent the data and the depth of channels for each internal mathematical module. In logic synthesis, different results can be obtained by changing the parameters according to the requirements of different wavelet. Take the (5, 3) filter commonly used in image processing as an example to illustrate the wavelet transform kernel method that realizes the filter based on the recombination characteristics of FPGA. The experimental results show that the lifting wavelet transform nuclear energy designed by FPGA can meet the requirements of different occasions and different operations.

**LS ****W****avelet ****T****ransform ****T****heory**

The process of LS transformation is shown in figure 1. The inverse transformation is the same as the forward transformation, but in the opposite order. The time discrete filter can be represented by its multinomial matrix, which is obtained by the Z transformation of the odd and even sampling sequence of the impulse response. The essence of LS wavelet transform is to decompose the classical wavelet filter using Euclidean algorithm.

*figure 1 forward LS transformation*

A time discrete filter H (z) is represented by a polynomial as follows:

He (z) and Ho (z) are obtained respectively from the odd and even coefficients. Analysis filter H (z) and G (z) represent low pass and high pass respectively, and are expressed as polyphase matrix:

P (z) can be simulated as an analytical filter. According to Euclidean algorithm, P (z) and P (z) can be decomposed into:

The above decomposition is not unique, there may be several pairs of {si(z)} and {ti(z)} filters, but all the choices for calculating DWT are equivalent.

**Realization of FPGA and ****L****ifting ****C****ore**

**FPGA and ****R****efactoring ****F****eatures**

FPGA (Field Programmable Gate Array) is the result of the development of VL and SI technology and computer-aided design (CAD) technology. FPGA device has the advantages of high integration and small size, and it can achieve special application through user programming. FPGA generally consists of three kinds of programmable circuits and one SRAM for storing programming data. This three kinds of programmable circuit is, CLB (Configurable Logic Block), IOB (I/O Block) and IR (Interconnect Resource). As the application of wavelets is more and more extensive, it is of high application value and research value to realize the reconfigurable lifting frame wavelet transform core with FPGA's flexible structure. The design starts from the basic mathematical modules and logic modules, and adopts the bottom-up design method. All library modules are described with VHDL language, allowing the data channel size of each unit to be selected according to the design accuracy requirements. In order to meet the needs of different environments, it is required to change the channel layer depth of individual modules and consider the compatibility with other devices. The lifting method is combined with the characteristics of FPGA so that different lifting wavelet transform can meet the needs of different applications on FPGA.

*figure 2 ascending nuclear structures*

**The Realization of Lifting Wavelet Transform Kernel**

As shown in figure 1, LS transformation is a continuous and independent simple filtering operation process, which is the lifting step. The optimized lifting nuclear structure can be derived from FIG. 1. In recent years, image transmission based on JPEG2000 standard has become a hot topic, and different lifting wavelet transform structures have been proposed in many literatures.

However, most of these lifting structures only consider maneuverability, but ignore power consumption and flexibility. The lifting nuclear structure proposed in this article (FIG. 2) adopts a different bottom-up design method. The main feature is to specify a separate flow-through multiplication unit and two addition units. The multiplication element is mainly used to deal with the symmetry problem of filter coefficients, and the addition element is used to realize the transformation of analysis or synthesis.

It is important to note that all channel layers can be lined up with the library modules designed, so in order to ensure synchronization of the internal IP core data flow, the back and forth crossing must be considered. For example, a multiplier has been placed in the addition output to allow normalization of the results of the lifting step. With this design method, the highest data accuracy and the fastest running speed can be obtained. In addition, integer mathematical units are easier to perform deep flow operations and achieve high data throughput. The structure presented in FIG. 2 takes into account both maneuverability and flexibility of application, and reduces power consumption due to increased operating speed.

**Logical Synthesis Result**

Firstly, using VHDL language to describe the basic mathematical module of reconfigurable logic module design and the transformation of the nuclear structure, and then do the fuction simulution to implement the required transformation in MAX + PLUS Ⅱ integration environment, finally step is the FPGA logic synthesis. The structure designed on FLEX10K of Altera1 company has obtained satisfactory results through logical synthesis, as shown in table 1. The results in table 1 are directly obtained by logical synthesis without considering the delay caused by various objective factors. More accurate timing analysis can be carried out in the installation and operation process after the steps of the design process. In addition, in order to obtain complete analysis results, power consumption should be estimated by referring to the indicators provided by the FPGA manufacturer. Programmable devices with low power consumption should be selected to better meet the requirements of different use environments. In (5, 3) filter as an example, the calculation of (5, 3) wavelet need four nuclear superposition, the proposed structure to calculate forward or reverse (5, 3) DWT, the 1400 x 1400 pixels per frame adopts 15 hits and 12 synthesis filter coefficient, in the clock frequency, 5 layers of decomposition and reconstruction, can deal with 25 frames per second image, power consumption is 267.6 mW.

*table 1 lifting nuclear synthesis results*

**Conclusion**

The reconfigurable lifting core structure is designed from the bottom up to ensure maximum reusability and reconfiguration. Simulation results show that the structure of lifting wavelet transform kernel has achieved good results in terms of processing power and power consumption, especially in terms of processing speed, which can meet the real-time requirements of image processing. The further development in the future is to add more free parameters into the basic arithmetic module, so as to ensure better operability of the structure, reduce power consumption, meet the needs of different applications, and have practical significance to reduce equipment cost and improve efficiency.

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