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Apr 16 2019

NAND512W3A2DN6E Datasheet PDF – NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 48-Pin TSOP Tray

Product Overview

Product Category:

Memory

Kynix Part #:

KY32-NAND512W3A2DN6E

Manufacturer Part#:

NAND512W3A2DN6E

Manufacturer

Micron Technology Inc.

Description:

IC FLASH 512MBIT 48TSOP

Package:

48-TFSOP (0.724", 18.40mm Width)

Datasheet:

NAND512W3A2DN6E Datasheet

Stock:

Yes

Quantity:

1928 PCS

NAND512W3A2DN6E Images are for reference only:

NAND512W3A2DN6E

 

Product Specifications

Product Category

Memory

Manufacturer

Micron Technology Inc.

Series

-

Packaging

Tray

Basic Package Type

Lead-Frame SMT

Package Family Name

SOP

Package Description

Thin Small Outline Package

REACH Compliant

Yes

EU RoHS Compliant

Yes

China RoHS Compliant

Yes

Cell Type

NAND

Command Compatible

No

Block Organization

Symmetrical

Boot Block

No

Lead Shape

Gull-wing

Architecture

Sectored

Access Time-Max

12000.0 ns

Address Bus Width

26 bit

HTSUSA

8542320071

Maximum Operating Current

30mA

Maximum Erase Time

0.003s/Block

Maximum Page Access Time

12000 ns

Maximum Programming Time

0.7   ms/Page

ECCN

3A991.b.1.a

ECC Support

Yes

Erase Suspend/Resume Modes Support

No

JESD-30 Code

R-PDSO-G48

JESD-609 Code

e3

Memory Width

8

Memory Density

5.12753664E8 bit

Memory Type

Non-Volatile

Memory Format

FLASH

Memory IC Type

FLASH

Number of Terminals

48

Number of Functions

1

Number of Words

6.7108864E7 words

Number of Words Code

64 M

Number of Bits per Word

8 bit

Reflow Solder Time

30 Sec

Organization

64MX8

Operating Mode

ASYNCHRONOUS

Operating Temperature-Min

-40.0 ºC

Operating Temperature-Max

85.0 ºC

Parallel/Serial

PARALLEL

Page Size

512byte

Package Body Material

PLASTIC/EPOXY

Package Code

TSOP1

Package Shape

RECTANGULAR

Package Style

SMALL OUTLINE, THIN PROFILE

Peak Reflow Temperature

260 ºC

Program Current

30 mA

Programming Voltage

3 V

Radiation Hardening

No

Seated Height-Max

1.2 mm

Standard

J-STD-020D

Supply Voltage-Nom

3.0 V

Supply Voltage-Min

2.7 V

Supply Voltage-Max

3.6 V

Surface Mount

Yes

Sector Size

16 Kbyte x 4096

Support of Page Mode

Yes

Simultaneous Read/Write Support

No

Support of Common Flash Interface

No

Typical Operating Supply Voltage

3 | 3.3V

Technology

CMOS

Temperature Grade

INDUSTRIAL

Terminal Finish

Tin (Sn)

Terminal Form

GULL   WING

Terminal Pitch

0.5  mm

Terminal Position

DUAL

Timing Type

Asynchronous

Length

18.4 mm

Width

12.0 mm

Height

1 mm

PCB

48

Pin Count

48

Pin Pitch

0.5 mm

 NAND512W3A2DN6E Datasheet PDF Download:

NAND512W3A2DN6E Datasheet PDF

Product Description

Product Description

Fig 1.

Logic Block Diagram

Logic Block Diagram

Fig 2.

Logic Diagram

Logic Diagram

Fig 3.

TSOP48 Connections - x8 devices

TSOP48 Connections

Fig 4.

Ordering Information Scheme

Ordering Information

Table1.

Description

The NAND flash 528-byte/264-word page is a family of non-volatile flash memories that uses the single level cell (SLC) NAND technology. It is referred to as the small page family.

The NAND512xxA2D devices have a density of 512 Mbits. They operate with either a 1.8 V or 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words(256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the data input/output signals on a multiplexed x8 or x16 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

To extend the lifetime of NAND flash devices it is mandatory to implement an error correction code (ECC). The use of ECC correction allows them to achieve up to 100,000 program/erase cycles for each block. A write protect pin is available to give a hardware protection against program and erase operations.

The devices feature an open-drain ready/busy output that can be used to identify if the program/erase/read (P/E/R) controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor.

A Copy Back command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed.

The NAND512xxA2D devices are available in the TSOP48 (12 x 20 mm) and VFBGA63 (9 x 11 x 1.05 mm) packages.

The NAND512xxA2D devices are available in two different versions:

No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read feature allows to download up to all the pages in a block with one read command and addressing only the first page to read

• With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between more active memories that are simultaneously active as Chip Enable transitions during latency do not stop read operations. Program and erase operations are not interrupted by Chip Enable transitions. 

And come with two security features:

• OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently. The access sequence and further details about this feature are subject to an NDA (non disclosure agreement)

• Serial number (unique identifier), which enables each device to be uniquely identified. It is subject to an NDA and is, therefore, not described in the datasheet.

Features

• High density SLC NAND flash memories

512 Mbit memory array

Cost effective solutions for mass storage applications

• NAND interface

x8 or x16 bus width

Multiplexed address/data

• Supply voltage: 1.8 V, 3 V

• Page size

x8 device: (512 + 16 spare) bytes

x16 device: (256 + 8 spare) words

• Block size

x8 device: (16 K + 512 spare) bytes

x16 device: (8 K + 256 spare) words

• Page read/program

Random access: 12 µs (3 V)/15 µs (1.8 V) (max)

Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)

Page program time: 200 µs (typ)

• Copy back program mode

• Fast block erase: 1.5 ms (typ)

• Status register

• Electronic signature

• Chip Enable ‘don’t care’

• Hardware data protection: program/erase locked during power transitions

• Security features

OTP area

Serial number (unique ID)

• Data integrity

100,000 program/erase cycles (with ECC)

10 years data retention

• RoHS compliant packages

• Development tools

Error correction code models

Bad blocks management and wear leveling algorithms

Hardware simulation models 

Other data sheets within the file:

Datasheet

NAND512W3A2DN6E Datasheet

NAND512W3A2DN6E Datasheet


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