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Apr 18 2019

MPC866PCZP100A Datasheet PDF - IC MPU MPC8XX 100MHZ 357BGA POWER QUICC

Product Overview

Product Category:Embedded - Microprocessors

Kynix Part #:

KY32-MPC866PCZP100A

Manufacturer Part#:

MPC866PCZP100A

Manufacturer

NXP USA Inc.

Description:

IC MPU MPC8XX POWER QUICC I HIP6W 100MHZ 357BGA

Package:

PBGA-357s

Datasheet:

MPC866PCZP100A Datasheet

Stock:

Yes

Quantity:

728 PCS

MPC866PCZP100A Images are for reference only:

MPC866PCZP100A Image

Product Specifications 

Categories

Integrated Circuits (ICs)

Embedded - Microprocessors

Series

MPC8xx

Brand

NXP / Freescale

Packaging

Tray

Part Status

Obsolete

Processor Series

PowerQUICC

Core Processor

MPC8xx

Interface Type

Ethernet, I2C, SPI, UART

L1 Cache Instruction Memory

16 kB

L1 Cache Data Memory

8 kB

Memory Type

L1 Cache

Mounting Style

SMD/SMT

Maximum Clock Frequency

100 MHz

Number of Cores/Bus Width

1 Core, 32-Bit

Number of Timers/Counters

4 x 16 bit

Speed

100MHz

Co-Processors/DSP

Communications; CPM

RAM Controllers

DRAM

Graphics Acceleration

No

Display & Interface Controllers

 -

Ethernet

10 Mbps (4), 10/100 Mbps (1)

SATA

-

USB

-

Voltage - I/O

3.3V

Operating Supply Voltage

1.8 V

Operating Temperature

-40°C ~ 100°C (TA)

Security Features

-

Package / Case

357-BBGA

Supplier Device Package

357-PBGA (25x25)

Additional Interfaces

HDLC/SDLC, I²C, IrDA, PCMCIA, SPI, TDM, UART/USART

Base Part Number

MPC866

Tradename

PowerQUICC

Watchdog Timers

Watchdog Timer

Unit Weight

0.079984 oz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Moisture Sensitivity Level (MSL)

3 (168 Hours)

MPC866PCZP100A Datasheet PDF Download:

MPC866PCZP100A Datasheet PDF

Block Diagram

MPC866P Block Diagram

Fig. 1 MPC866P Block Diagram

Description

The MPC866 is a derivative of Freescale’s MPC860 PowerQUICC family of devices. It is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC866 provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family.

Features

Embedded single-issue, 32-bit PowerPC™ core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs)

a. The core performs branch prediction with conditional prefetch, without conditional execution

b.4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache

c. MMUs with 32-entry TLB, fully associative instruction and data TLBs

d. MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups.

e. Advanced on-chip-emulation debug mode

The MPC866/859 provides enhanced ATM functionality over that of the MPC860SAR. The MPC866/859 adds major new features available in 'enhanced SAR' (ESAR) mode, including the following:

a. Improved operation, administration, and maintenance (OAM) support

b. OAM performance monitoring (PM) support

c. Multiple APC priority levels available to support a range of traffic pace requirements

d. ATM port-to-port switching capability without the need for RAM-based microcode

e. Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability

f. Optional statistical cell counters per PHY

Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)

Thirty-two address lines

Memory controller (eight banks)

a. Contains complete dynamic RAM (DRAM) controller

b. Each bank can be a chip select or RAS to support a DRAM bank

c. Up to 30 wait states programmable per memory bank

d. Glueless interface to page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other memory devices.

One serial peripheral interface (SPI)

a. Supports master and slave modes

b. Supports multiple-master operation on the same bus

One inter-integrated circuit (I2C) port

a. Supports master and slave modes

b. Multiple-master environment support

Time slot assigner (TSA) (MPC859DSL does not have TSA.)

a. Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation

b. Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined

c. 1- or 8-bit resolution

d. Allows independent transmit and receive routing, frame synchronization, and clocking

e. Allows dynamic changes

f. On MPC866P and MPC866T, can be internally connected to six serial channels (four SCCs and two SMCs); on MPC859P and MPC859T, can be connected to three serial 

channels (one SCC and two SMCs).

Parallel interface port (PIP)

a. Centronics interface support

b. Supports fast connection between compatible ports on MPC866/859 or MC68360

PCMCIA interface

a. Master (socket) interface, compliant with PCI Local Bus Specification (Rev 2.1)

b. Supports one or two PCMCIA sockets whether ESAR functionality is enabled

c. Eight memory or I/O windows supported

Debug interface

a. Eight comparators: four operate on instruction address, two operate on data address, and two operate on data.

Normal high and normal low power modes to conserve power

1.8 V core and 3.3 V I/O operation with 5-V TTL compatibility

357-pin plastic ball grid array (PBGA) package

Operation up to 133 MHz

Other data sheets within the file:

Datasheet

MPC866PCZP100A Datasheet

MPC866PCZP100A Datasheet

Application Notes

Migrating from the MPC860 to the MPC866 PowerQUICC

Migrating from the MPC860 to the MPC866 PowerQUICC

Using the CodeTEST Probe with Freescale MPC8xx Processors

Using the CodeTEST Probe with Freescale MPC8xx Processors

Images

Functional Block Diagram - Large

Functional Block Diagram - Large

Mechanical Outline Drawing  

Mechanical Outline Drawing

Technical Resources

AN2810 Supporting Files

AN2810 Supporting Files

Introduction to the Plastic Ball Grid Array (PBGA)

Introduction to the Plastic Ball Grid Array (PBGA)

Test/Quality Data

Material Composition

Material Composition

RoHS Certificate of Analysis

RoHS Certificate of Analysis

Statement on EU REACH Provisions

Statement on EU REACH Provisions


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