Product Overview
Product Category: | Embedded - Microprocessors |
Kynix Part #: | KY32-MPC8541EVTAPF |
Manufacturer Part#: | MPC8541EVTAPF |
Manufacturer | NXP USA Inc. |
Description: | IC MPU MPC85XX 833MHZ 783FCBGA |
Package: | 783-BBGA, FCBGA |
Datasheet: | |
Stock: | Yes |
Quantity: | 105 PCS |
MPC8541EVTAPF Images are for reference only:
Product Specifications
Categories | Integrated Circuits (ICs) Embedded - Microprocessors |
Series | MPC85xx |
Status | Not For New Designs |
Core Processor | PowerPC e500 |
Co-Processors/DSP | Security; SEC |
Data Bus Width | 32 Bit |
Device Core | PowerQUICC III |
Display & Interface Controllers | - |
Ethernet | 10/100/1000 Mbps (2) |
Graphics Acceleration | No |
I/O Voltage | 2.5, 3.3 V |
Instruction Type | Floating Point |
Instruction Set Architecture | RISC |
Lead Finish | Tin/Silver |
Max Processing Temp | 260 Cel |
Maximum Clock Frequency | 833 MHz |
Maximum Speed | 833 MHz |
Mounting | Surface Mount |
Number of Cores/Bus Width | 1 Core, 32-Bit |
Operating Supply Voltage | 1.2 V |
Operating Temperature | 0 to 105 °C |
Packaging | Tray |
Pin Count | 783 |
Product Dimensions | 29 x 29 x 3.25 mm |
Package / Case | 783-BBGA, FCBGA |
Supplier Device Package | 783-FCPBGA (29x29) |
RAM Controllers | DDR, SDRAM |
Speed | 833MHz |
Security Features | Cryptography, Random Number Generator |
SATA | - |
USB | - |
Voltage - I/O | 2.5V, 3.3V |
Watchdog Timers | Watchdog Timer |
Base Part Number | MPC8541 |
Additional Interfaces | DUART, I²C, PCI |
Brand | NXP / Freescale |
Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
MPC8541EVTAPF Datasheet PDF Download:
Block Diagram
Fig. 1 MPC8541E Block Diagram
Description
The MPC8541E PowerQUICC® III host processor integrates a wide range of advanced NXP® technologies, modular cores and peripherals. Leveraging Our system-on-chip (SoC) PowerQUICC III platform architecture, the MPC8541E combines a high-performance e500 core and communications peripheral technology to balance processor performance with I/O system throughput. The processor is designed to offer clock speeds scaling from 533 MHz to 1 GHz.
Our MPC8541E processor integrates a high-performance e500 core built on Power Architecture® technology, designed to reduce power consumption and offer a more balanced approach to processing than traditional processor architectures. The MPC8541E device's high level of integration helps simplify board design and enhances system-level bandwidth and performance. In addition, the MPC8541E features an integrated security engine, a double data rate SDRAM (DDR SDRAM) memory controller, dual Gigabit Ethernet (GbE) controllers, dual 10/100 Ethernet, a four-channel direct memory access (DMA) controller, dual asynchronous receiver/transmitters (DUART) and a 64-bit PCI controller that can also serve as two 32-bit PCI ports. Dual on-chip PCI support provides a cost-effective alternative to separate, discrete PCI bridges and chipsets for I/O-intensive applications that require multiple PCI interfaces. The MPC8541E also provides a local bus controller, dual I²C support, and serial peripheral interface (SPI).
The MPC8541E processor features a security engine that supports DES, 3DES, MD-5, SHA-1, AES and ARC-4 encryption algorithms, as well as offering a public key accelerator and on-chip random number generator. This embedded security core is derived from Our security coprocessor product line and offers the same DMA and parallel processing capabilities, as well as the ability to perform single-pass encryption and authentication as required by widely used security protocols, such as IPsec and 802.11i. Integrated security makes the MPC8541E an optimal integrated processor solution for applications that require security features in concert with high performance and low system-level cost.
Features
l Communications processor module for peripheral processing tasks
l Integrated security engine
l Multiple-PCI interface support
l High-performance e500 core
l Lower power consumption
l Flexible SoC platform for fast time to market
l Simplified board design
Other data sheets within the file:
Datasheet | |
MPC8541E |  |
Application Notes | |
AN2583, Programming the PowerQUICC® III/PowerQUICC II Pro DDR SDRAM Controller - Application Note (REV 11) |  |
AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes (REV 2) |  |
PowerQUICC® III MPC8555E and MPC8541E Bring-Up Guidelines (REV 5) |  |
Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations (REV 1) |  |
Communicating via HDLC over a TDM Interface with a QUICC Engine™ UCC (REV 0) |  |
PowerQUICC™ HDLC Support and Example Code (REV 0) |  |
PowerQUICC®™ UPM Configuration (REV 2) |  |
MPC603e and e500 Register Model Comparison (REV 1) |  |
PowerQUICC™ Data Cache Coherency (REV 0) |  |
Coherency and Synchronization Requirements for PowerQUICC™ III (REV 1) |  |
Error Correction and Error Handling on PowerQUICC (TM) III Processors (REV 0) |  |
Migrating from PowerQUICC® II to PowerQUICC III (REV 2) |  |
PowerQUICC® III Power Measurements Application Note (REV 0) |  |
Migration from MPC8540 or MPC8541E to MPC8548E (REV 0) |  |
Errata | |
Errata to PowerPC e500 Core Family Reference Manual, Rev. 1 |  |
Recommended Documentation | |
MPC8541E Data Sheet (REV 4.2) |  |
MPC8541E Fact Sheet (REV 7) |  |
MPC8555E Reference Manual (REV 2) |  |
Test/Quality Data | |
Material Composition |  |
Statement on EU REACH Provisions |  |
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