Home  Embedded - Microprocessors

Apr 3 2019

MPC8541EVTAJD Datasheet PDF - IC MPU MPC85XX 533MHZ 783FCBGA

Product Overview

Product Category:

Embedded - Microprocessors

Kynix Part #:

KY32-MPC8541EVTAJD

Manufacturer Part#:

MPC8541EVTAJD

Manufacturer

NXP / Freescale

Description:

Microprocessers - MPU PQ 37 LITE 8555E

Package:

783-BBGA, FCBGA

Datasheet:

MPC8541EVTAJD Datasheet

Stock:

Yes

Quantity:

504 PCS


MPC8377VRAJFA Images are for reference only:

MPC8541EVTAJD Image

Product Specifications


Categories

Integrated Circuits (ICs)

Embedded - Microprocessors

Core Processor

PowerPC e500

Co-Processors/DSP

Security; SEC

Device Core

PowerQUICC III

Ethernet

10/100/1000 Mbps

Max Processing Temp

260

Mounting Type

Surface Mount

MSL Level

3

Number of CPU Cores

1

Number of Cores/Bus Width

1 Core, 32-Bit

I/O Voltage

2.5, 3.3 V

Instruction Set Architecture

RISC

Series

MPC85xx

Package / Case

783-BBGA, FCBGA

Packaging

Tray

Part Status

Not For New Designs

Speed

533MHz

RAM Controllers

DDR, SDRAM

Graphics Acceleration

No

Display & Interface Controllers

-

Ethernet

10/100/1000 Mbps

SATA

-

USB

-

Operating Temperature

0°C ~ 105°C (TA)

Operating Supply Voltage

1.2 V

Security Features

Cryptography, Random Number Generator

Pin Count

783

Product Dimensions

29 x 29 x 3.25 mm

Qualification 

AEC-Q100

Supplier Device Package

783-FCPBGA (29x29)

Interface Type

 Ethernet, I2C, PCI, SPI, UART

Additional Interfaces

DUART, I²C, PCI

Base Part Number

MPC8541

Lead Finish

Tin/Silver

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Moisture Sensitivity Level (MSL)

3 (168 Hours)

ECCN

5A002.A.1

HTSN

8542310001

SCHEDULE B

8542310000


MPC8377VRAJFA Datasheet PDF Download: 

MPC8377VRAJFA Datasheet PDF

Block Diagram

MPC8541E Block Diagram

Fig. 1 MPC8541E Block Diagram


Description

MPC8541E combines a high-performance e500 core and communications peripheral technology to balance processor performance with I/O system throughput. The processor is designed to offer clock speeds scaling from 533 MHz to 1 GHz. Freescale's MPC8541E processor integrates a high-performance e500 core built on Power Architecture technology, designed to reduce power consumption and offer a more balanced approach to processing than traditional processor architectures. The MPC8541E device's high level of integration helps simplify board design and enhances system-level bandwidth and performance. In addition, the MPC8541E features an integrated security engine, a double data rate SDRAM (DDR SDRAM) memory controller, dual Gigabit Ethernet (GbE) controllers, dual 10/100 Ethernet, a four-channel direct memory access (DMA) controller, dual asynchronous receiver/transmitters (DUART) and a 64-bit PCI controller that can also serve as two 32-bit PCI ports. Dual on-chip PCI support provides a cost-effective alternative to separate, discrete PCI bridges and chipsets for I/O-intensive applications that require multiple PCI interfaces. The MPC8541E also provides a local bus controller, dual I²C support, and serial peripheral interface (SPI). The MPC8541E processor features a security engine that supports DES, 3DES, MD-5, SHA-1, AES and ARC-4 encryption algorithms, as well as offering a public key accelerator and on-chip random number generator. This embedded security core is derived from Freescale's security coprocessor product line and offers the same DMA and parallel processing capabilities, as well as the ability to perform single-pass encryption and authentication as required by widely used security protocols, such as IPsec and 802.11i. Integrated security makes the MPC8541E an optimal integrated processor solution for applications that require security features in concert with high performance and low system-level cost.

Features

The following lists an overview of the MPC8541E feature set.

• Embedded e500 Book E-compatible core

— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture

— Dual-issue superscalar, 7-stage pipeline design

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection

— Lockable L1 caches—entire cache or on a per-line basis

— Separate locking for instructions and data

— Single-precision floating-point operations

— Memory management unit especially designed for embedded applications

— Enhanced hardware and software debug support

— Dynamic power management

— Performance monitor facility

• Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller, and a set of crypto Execution Units (EUs). 

The Execution Units are:

— Public Key Execution Unit (PKEU) supporting the following:

– RSA and Diffie-Hellman

– Programmable field size up to 2048-bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511-bits

— Data Encryption Standard Execution Unit (DEU)

– DES, 3DES

– Two key (K1, K2) or Three Key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced Encryption Standard Unit (AESU)

– Implements the Rinjdael symmetric key cipher

– Key lengths of 128, 192, and 256 bits.Two key

– ECB, CBC, CCM, and Counter modes

— ARC Four execution unit (AFEU)

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message Digest Execution Unit (MDEU)

– SHA with 160-bit or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random Number Generator (RNG)

— 4 Crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units via an integrated controller

– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes

• High-performance RISC CPM

— Two full-duplex fast communications controllers (FCCs) that support the following protocol:

– IEEE Std 802.3™/Fast Ethernet (10/100)

— Serial peripheral interface (SPI) support for master or slave

— I2C bus controller

— General-purpose parallel ports—16 parallel I/O lines with interrupt capability

• 256 Kbytes of on-chip memory

— Can act as a 256-Kbyte level-2 cache

— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays

— Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— SRAM operation supports relocation and is byte-accessible

— Cache mode supports instruction caching, data caching, or both

— External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing).

— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)

— Supports locking the entire cache or selected lines

– Individual line locks set and cleared through Book E instructions or by externally mastered transactions

— Global locking and flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be flash cleared separately

— Read and write buffering for internal bus accesses

• Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 32-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

– Three inbound windows plus a configuration window on PCI

– Four inbound windows

– Four outbound windows plus default translation for PCI

• DDR memory controller

— Programmable timing supporting first generation DDR SDRAM

— 64-bit data interface, up to MHz data rate

— Four banks of memory supported, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports

— Full ECC support

— Page mode support (up to 16 simultaneous open pages)

— Contiguous or discontiguous memory mapping

— Sleep mode support for self refresh DDR SDRAM

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

• Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller

— Four global high resolution timers/counters that can generate interrupts

— Supports additional internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs

— Interrupt summary registers allow fast identification of interrupt source

• Two I2

C controllers (one is contained within the CPM, the other is a stand-alone controller which is not part of the CPM)

— Two-wire interface

— Multiple master support

— Master or slave I2C mode support

— On-chip digital filtering rejects spikes on the bus

• Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the stand-alone I2C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I2C addressing mode

— Data integrity checked with preamble signature and CRC

• DUART

— Two 4-wire interfaces (RXD, TXD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 166 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller

— Three protocol engines available on a per chip select basis:

– General purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

• Two Three-speed (10/100/1000)Ethernet controllers (TSECs)

— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers

— Support for Ethernet physical interfaces:

– 10/100/1000 Mbps IEEE 802.3 GMII

– 10/100 Mbps IEEE 802.3 MII

– 10 Mbps IEEE 802.3 MII

– 1000 Mbps IEEE 802.3z TBI

– 10/100/1000 Mbps RGMII/RTBI

— Full- and half-duplex support

— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100 programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— 2-Kbyte internal transmit and receive FIFOs

— MII management interface for control and status

— Programmable CRC generation and checking

• OCeaN switch fabric

— Three-port crossbar packet switch

— Reorders packets from a source based on priorities

— Reorders packets to bypass blocked packets

— Implements starvation avoidance algorithms

— Supports packets with payloads of up to 256 bytes

• Integrated DMA controller

— Four-channel controller

— All channels accessible by both local and remote masters

— Extended DMA functions (advanced chaining and striding capability)

— Support for scatter and gather transfers

— Misaligned transfer capability

— Interrupt on completed segment, link, list, and error

— Supports transfers to or from any local memory or I/O port

— Selectable hardware-enforced coherency (snoop/no-snoop)

— Ability to start and flow control each DMA channel from external 3-pin interface

— Ability to launch DMA from single write transaction

• PCI Controllers

— PCI 2.2 compatible

— One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz

— Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one can be an agent

— 64-bit dual address cycle (DAC) support

— Supports PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses

— Supports posting of processor-to-PCI and PCI-to-memory writes

— PCI 3.3-V compatible

— Selectable hardware-enforced coherency

— Selectable clock source (SYSCLK or independent PCI_CLK)

• Power management

— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O

— Supports power save modes: doze, nap, and sleep

— Employs dynamic power management

— Selectable clock source (sysclk or independent PCI_CLK)

• System performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

• System access port

— Uses JTAG interface and a TAP controller to access entire system memory map

— Supports 32-bit accesses to configuration registers

— Supports cache-line burst accesses to main memory

— Supports large block (4-Kbyte) uploads and downloads

— Supports continuous bit streaming of entire block for fast upload and download

• IEEE Std 1149.1™-compatible, JTAG boundary scan

• 783 FC-PBGA package

— Fast memory access via JTAG port

— 2.5-V SSTL2 compatible I/O

Other data sheets within the file:

Datasheet

MPC8541EVTAJD PDF

MPC8541EVTAJD PDF

Application Notes

e300 (MPC603e) and e500 Register Model Comparison

e300 (MPC603e) and e500 Register Model Comparison PDF

e500 Software Optimization Guide (eSOG)

e500 Software Optimization Guide (eSOG) PDF

Error Correction and Error Handling on PowerQUICC III Processors

Error Correction and Error Handling on PowerQUICC III Processors PDF

Hardware and Layout Design Considerations for DDR Memory Interfaces

Hardware and Layout Design Considerations for DDR Memory Interfaces PDF

Initializing the TSEC Controller

Initializing the TSEC Controller PDF

Migrating from e300- to e500-Based Integrated Devices

Migrating from e300- to e500-Based Integrated Devices PDF

Migrating from e600- to e500-Based Integrated Devices

Migrating from e600- to e500-Based Integrated Devices PDF

Migrating from PowerQUICC II to PowerQUICC III

Migrating from PowerQUICC II to PowerQUICC III PDF

Migration from MPC8540 or MPC8541E to MPC8548E

Migration from MPC8540 or MPC8541E to MPC8548E PDF

PowerQUICC Data Cache Coherency

PowerQUICC Data Cache Coherency PDF

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines PDF

PowerQUICC UPM Configuration

PowerQUICC UPM Configuration PDF

Programming the PowerQUICC III/PowerQUICC II Pro DDR SDRAM Controller

Programming the PowerQUICC III/PowerQUICC II Pro DDR SDRAM Controller PDF

SEC 2.0 Descriptor Programmer's Guide

SEC 2.0 Descriptor Programmer's Guide PDF

Setting Up TSEC Hash Tables

Setting Up TSEC Hash Tables PDF

Using the Serial RapidIO Messaging Unit on PowerQUICC III

Using the Serial RapidIO Messaging Unit on PowerQUICC III PDF

Watchdog Timer for e500

Watchdog Timer for e500 PDF

EOL

Product Discontinuation Notification

Product Discontinuation Notification PDF


0 comment

Leave a Reply

Your email address will not be published.

 
 
   
Rating: