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Nov 2 2019

MPC8360VVAGDGA Datasheet PDF - IC MPU MPC83XX 740TBGA NXP

Product Overview

Product Category:

Embedded - Microprocessors

Kynix Part #:

KY32-MPC8360VVAGDGA

Manufacturer Part#:

MPC8360VVAGDGA

Manufacturer

NXP USA Inc.

Description:

IC MPU MPC83XX 400MHZ 740TBGA

Package:

740-LBGA

Datasheet:

MPC8360VVAGDGA Datasheet

Stock:

Yes

Quantity:

130 PCS


MPC8360VVAGDGA Images are for reference only:

MPC8360VVAGDGA Image 

Product Specifications 

Categories

Integrated Circuits (ICs)

Embedded - Microprocessors

Series

MPC83xx

Status

Active

EU RoHS Compliant

Yes

REACH Compliant

Yes

China RoHS Compliant

Yes

Package Description

37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, TBGA-740

Address Bus Width

32.0

Brand

NXP / Freescale

Boundary Scan

Yes

Base Part Number

MPC8360

Core Processor

PowerPC e300

Co-Processors/DSP

Communications; QUICC Engine

Clock Frequency-Max

66.67 MHz

DAC Channels

No

DMA Channels

No

Display & Interface Controllers

-

Ethernet

10/100/1000Mbps (1)

External Data Bus Width

32.0

Format

FLOATING POINT

Graphics Acceleration

No

Halogen Free

Halogen Free

Integrated Cache

Yes

Instruction Set Architecture

RISC

I/O Voltage

1.8, 2.5, 3.3 V

JESD-30 Code

S-PBGA-B740

JESD-609 Code

e2

Low Power Mode

Yes

MCU Family

PowerQUICC

MCU Series

PowerQUICC II Pro

Moisture Sensitive

Yes

Mounting Style

SMD/SMT

Max I/O Voltage

3.3 V

Number of Cores

1

Number of Pins

740

Length

37.5 mm

Width

37.5 mm

Operating Temperature

0°C ~ 105°C (TA)

Packaging

Tray

Product Category

PowerQUICC II Pro

Product Dimensions

37.5 x 37.5 x 1.05 mm

Package / Case

740-LBGA

Supplier Device Package

740-TBGA (37.5x37.5)

Package Body Material

PLASTIC/EPOXY

Package Code

LBGA

Package Equivalence Code

BGA740,37X37,40

Package Shape

SQUARE

Package Style

GRID ARRAY, LOW PROFILE

Peak Reflow Temperature (Cel)

260

Power Supplies

1.8/2.5,3.3 V

Qualification Status

Not Qualified

RAM Controllers

DDR, DDR2

REACH SVHC

No SVHC

Radiation Hardening

No

RoHS

Compliant

Rohs Code

Yes

Risk Rank

5.15

Speed

400 MHz

Seated Height-Max

1.69 mm

Supply Voltage-Max

1.26 V

Supply Voltage-Min

1.14 V

Supply Voltage-Nom

1.2 V

Subcategory

Microprocessors

Technology

CMOS

Temperature Grade

OTHER

Terminal Finish

TIN COPPER/TIN SILVER

Terminal Form

BALL

Terminal Pitch

1 mm

Terminal Position

BOTTOM

Time@Peak Reflow Temperature-Max (s)

40

USB

USB 1.x (1)

Lead Free Status / RoHS Status

Lead free / ROHS3 Compliant

Moisture Sensitivity Level (MSL)

3 (168 Hours)

Additional Interfaces

DUART, HDLC, I²C, PCI, SPI, UART

uPs/uCs/Peripheral ICs Type

MICROPROCESSOR, RISC


MPC8360VVAGDGA Datasheet PDF Download:

MPC8360VVAGDGA Datasheet PDF

Block Diagram

 MPC8360E Block Diagram

Fig. 1 MPC8360E Block Diagram

Description

The MPC8360E PowerQUICC II Pro family of integrated communications processors is a next-generation extension of the popular PowerQUICC II line containing cores built on Power Architecture technology. The MPC8360E family incorporates a next-generation communications engine, the QUICC Engine, supporting a wide range of protocols, including Gigabit Ethernet (GbE) and OC-12 asynchronous transfer mode (ATM)/packet over SONET (POS). Additional enhancements include the e300 core (enhanced version of the 603e core with larger caches), scaling up to 667 MHz, a double data rate (DDR) memory controller and the integrated security engine. The MPC8360E PowerQUICC II Pro communications processor's advanced features make it suitable for today and tomorrow's wired and wireless access equipment, as well as small and medium enterprise networking equipment. Target applications include multitenant units (MTUs), DSL access multiplexers (DSLAMs), wireless basestations, multi-and fixed-subscriber access nodes, add/drop multiplexers and routers. The MPC8358E processor, a member of the MPC8360E PowerQUICC II Pro family, is pin-compatible with the MPC8360E. The MPC8358E offers a cost-effective, low-power processing solution that meets the performance requirements for broadband access applications, such as small-to-medium enterprise (SME) routers, low-end DSLAMs and IP private automatic branch exchange (PABX) systems.

Features

e300 core operating from 266 MHz to 667 MHz

  • 32-bit, high-performance superscalar core

  • 1,261 MIPS at 667 MHz; 503 MIPS at 266 MHz

  • Double-precision floating point, integer, load/store, system register branch processor units and 32 KB data and 32 KB instruction cache with line-locking support

QUICC Engine initially operating up to 500 MHz

  • Two 32-bit RISC controllers for flexible support of the communications peripherals

  • Eight unified communication controllers (UCCs) supporting the following protocols and interfaces

  • 10/100/1000 Mbps Ethernet

  • ATM SAR supporting AAL5, AAL2, AAL1,AAL0, TM 4.0 CBR,VBR, UBR traffic types, up to 64KB external connections

  • Inverse multiplexing for ATM (IMA)

  • POS up to 622 Mbps

  • Transparent

  • HDLC

  • Multilink, multiclass PPP

  • HDLC bus

  • UART

  • BISYNC

  • One multichannel communication controller (MCC) supporting

256 channels with up to eight TDMs

Transparent and HDLC mode per channel

Support for signaling system number 7 (SS7)

Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces

  • Two UTOPIA/POS interfaces supporting up to 128 multi-PHY each

  • Two serial peripheral interface (SPI)

  • Eight TDM interfaces (T1/E1)

Aggregate bandwidth of 64 kbps and 256 channels

Maximum of 16 Mbps and 256 channels on a single TDM link

2,048 bytes of SI RAM (1,024 entries)

Eight programmable strobes

Bit or byte resolution

Independent transmit and receive routing, frame synchronization

Supports T1, CEPT, T1/E1, T3/E3, pulse-code modulation highway, ISDNprimary/basic rate, Freescale interchip digital link (IDL) and user-defined TDM serial interfaces

  • 16 independent baud rate generators

  • Four independent 16-bit timers that can be interconnected as two 32-bit timers

  • Two SPI ports that can be configured as an Ethernet management port for management data input/output (MDIO), while the other can be configured for low-cost serial peripherals; the SPI also has a CPU mode that can be configured by the CPU and not through the QUICC Engine

  • USB interface (USB 2.0 full-/low-speed compatible)

  • DDR memory controller

Programmable timing supporting both DDR1 and DDR2 SDRAM

2 x 32-bit or 1 x 64-bit data interface; up to 333 MHz data rate

Four banks of memory, each up to 1 GB

Full ECC support

PCI interface

  • One 32-bit PCI 2.2 bus controller (3.3V I/O; up to 66 MHz)

Integrated security (MPC8360E and MPC8358E only)

  • Public key execution (RSA and Diffie-Hellman)

  • Data encryption standard execution (DES and 3DES)

  • Advanced encryption standard (AES) execution

  • ARC-4 execution (RC4-compatible algorithm)

  • Message digest execution (SHA, MD5, HMAC)

  • Random number generation (RNG)

Local bus controller

  • Multiplexed 32-bit address and data operating up to 133 MHz

  • 32-, 16- and 8-bit port sizes controlled by on-chip memory controller

Dual UART (DUART)

Dual I²C interfaces (master or slave mode)

Four-channel DMA controller

General-purpose parallel I/O

IEEE 1149.1 JTAG test access port

Package option: 37.5 mm x 37.5 mm 740 TBGA

Process technology: 130 nm CMOS

Voltage: 1.2-volt core voltage with 3.3 and 2.5-volt I/O

Other data sheets within the file:

Environmental Information

NXP RoHS3 Cert

NXP RoHS3 Cert

PCN Design/Specification

Copper Bond Wire Qualification 07/Sep/2014

Copper Bond Wire Qualification 07/Sep/2014

Technical Resources


AN2810 Supporting Files Autre

AN2810 Supporting Files Autre

Comparison of DDRx and SDRAM

Comparison of DDRx and SDRAM


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