MPC8309CVMAHFCA Datasheet PDF - IC MPU MPC83XX 417MHZ 489BGA Freescale Semiconductor - NXP

Product Overview

MPC8309CVMAHFCA Images are for reference only:

Product Specifications 

MPC8309CVMAHFCA Datasheet PDF Download:

Block Diagram

Fig 1. MPC8309 Block Diagram

Pin Assignments

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Description

The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and a 16/32-bit DDR2 memory controller with 8-bit ECC.

A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure.

Features

The major features of the device are as follows:

• e300c3 Power Architecture processor core

— Enhanced version of the MPC603e core

— High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times

— Floating-point, dual integer units, load/store, system register, and branch processing units

— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities

— Dynamic power management

— Enhanced hardware program debug features

— Software-compatible with Freescale processor families implementing Power Architecture technology

— Separate PLL that is clocked by the system bus clock

— Performance monitor

• QUICC Engine block

— 32-bit RISC controller for flexible support of the communications peripherals with the following features:

– One clock per instruction

– Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization

– 32-bit instruction object code

– Executes code from internal IRAM

– 32-bit arithmetic logic unit (ALU) data path

– Modular architecture allowing for easy functional enhancements

– Slave bus for CPU access of registers and multiuser RAM space

– 48 Kbytes of instruction RAM

– 16 Kbytes of multiuser data RAM

– Serial DMA channel for receive and transmit on all serial channels

— Five unified communication controllers (UCCs) supporting the following protocols and interfaces:

– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.

– IEEE Std. 1588™ support

– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)

– HDLC Bus (bit rate up to 10 Mbps)

– Asynchronous HDLC (bit rate up to 2 Mbps)

– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps

Other data sheets within the file:

Datasheets
MPC8309CVMAHFCA Datasheet
PCN Design/Specification
eSDHC Erratum A-009204; 837x, 8536, 8569, 830x, P1020, P1022, P2020, and P4080 Family of Devices
RE-INTRODUCING IEEE1588 SPECS TO MPC8309 DATA SHEET
MPC830x MAPBGA Product Family Copper Wire Bond Qualification
Test/Quality Data
Material Composition
RoHS Certificate of Analysis
Statement on EU REACH Provisions