Product Overview
Product Category: | Embedded - Microprocessors |
Kynix Part #: | KY32-MPC8309CVMAHFCA |
Manufacturer Part#: | MPC8309CVMAHFCA |
Manufacturer | Freescale Semiconductor - NXP |
Description: | IC MPU MPC83XX 417MHZ 489BGA |
Package: | 489-LFBGA |
Datasheet: | |
Stock: | Yes |
Quantity: | 433 PCS |
MPC8309CVMAHFCA Images are for reference only:
Product Specifications
Categories | Integrated Circuits (ICs) Embedded - Microprocessors |
Manufacturer | NXP USA Inc. |
Series | MPC83xx |
Packaging | Tray |
Part Status | Active |
Core Processor | PowerPC e300c3 |
Number of Cores/Bus Width | 1 Core, 32-Bit |
Speed | 417MHz |
Co-Processors/DSP | Communications; QUICC Engine |
RAM Controllers | DDR2 |
Graphics Acceleration | No |
Display & Interface Controllers | - |
Ethernet | 10/100Mbps (3) |
SATA | - |
USB | USB 2.0 (1) |
Voltage - I/O | 1.8V, 3.3V |
Operating Temperature | -40°C ~ 105°C (TA) |
Security Features | - |
Package / Case | 489-LFBGA |
Supplier Device Package | 489-PBGA (19x19) |
Additional Interfaces | CAN, DUART, I²C, MMC/SD, PCI, SPI, TDM |
Base Part Number | MPC8309 |
Mfr Package Description | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489 |
EU RoHS Compliant | Yes |
Status | Transferred |
Address Bus Width | 0.0 |
Bit Size | 32 |
Boundary Scan | YES |
Clock Frequency-Max | 66.67 MHz |
External Data Bus Width | 0.0 |
Format | FLOATING POINT |
Integrated Cache | YES |
JESD-30 Code | S-PBGA-B489 |
JESD-609 Code | e2 |
Low Power Mode | YES |
Moisture Sensitivity Level | 3 |
Number of Terminals | 489 |
Operating Temperature-Min | -40.0 Cel |
Operating Temperature-Max | 105.0 Cel |
Package Body Material | PLASTIC/EPOXY |
Package Code | LFBGA |
Package Equivalence Code | BGA489,23X23,32 |
Package Shape | SQUARE |
Package Style | GRID ARRAY, LOW PROFILE, FINE PITCH |
Peak Reflow Temperature (Cel) | 260 |
Power Supplies | 1 |
Qualification Status | Not Qualified |
Seated Height-Max | 1.61 mm |
Speed | 417.0 MHz |
Sub Category | Microprocessors |
Supply Voltage-Nom | 1.0 V |
Supply Voltage-Min | 0.95 V |
Supply Voltage-Max | 1.05 V |
Surface Mount | YES |
Technology | CMOS |
Temperature Grade | INDUSTRIAL |
Terminal Finish | TIN COPPER/TIN SILVER |
Terminal Form | BALL |
Terminal Pitch | 0.8 mm |
Terminal Position | BOTTOM |
Time@Peak Reflow Temperature-Max (s) | 40 |
Length | 19.0 mm |
Width | 19.0 mm |
MPC8309CVMAHFCA Datasheet PDF Download:
Block Diagram
Fig 1. MPC8309 Block Diagram
Pin Assignments
There is no relevant information available for this part yet.
Description
The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and a 16/32-bit DDR2 memory controller with 8-bit ECC.
A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure.
Features
The major features of the device are as follows:
• e300c3 Power Architecture processor core
— Enhanced version of the MPC603e core
— High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times
— Floating-point, dual integer units, load/store, system register, and branch processing units
— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
— Dynamic power management
— Enhanced hardware program debug features
— Software-compatible with Freescale processor families implementing Power Architecture technology
— Separate PLL that is clocked by the system bus clock
— Performance monitor
• QUICC Engine block
— 32-bit RISC controller for flexible support of the communications peripherals with the following features:
– One clock per instruction
– Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization
– 32-bit instruction object code
– Executes code from internal IRAM
– 32-bit arithmetic logic unit (ALU) data path
– Modular architecture allowing for easy functional enhancements
– Slave bus for CPU access of registers and multiuser RAM space
– 48 Kbytes of instruction RAM
– 16 Kbytes of multiuser data RAM
– Serial DMA channel for receive and transmit on all serial channels
— Five unified communication controllers (UCCs) supporting the following protocols and interfaces:
– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.
– IEEE Std. 1588™ support
– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)
– HDLC Bus (bit rate up to 10 Mbps)
– Asynchronous HDLC (bit rate up to 2 Mbps)
– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps
Other data sheets within the file: