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Apr 23 2019

MPC8306SCVMAFDCA Datasheet PDF – PowerPC e300c3 Microprocessor IC MPC83xx 1 Core, 32-Bit 333MHz 369-PBGA (19x19)

Product Overview

Product Category:

Embedded - Microprocessors

Kynix Part #:

KY32 - MPC8306SCVMAFDCA

Manufacturer Part#:

MPC8306SCVMAFDCA

Manufacturer

Freescale Semiconductor - NXP

Description:

IC MPU MPC83XX 333MHZ 369BGA

Package:

369-LFBGA

Datasheet:

MPC8306SCVMAFDCA Datasheet

Stock:

Yes

Quantity:

104 PCS

MPC8306SCVMAFDCA Images are for reference only:

MPC8306SCVMAFDCA

Product Specifications

Product Category

Embedded - Microprocessors

Manufacturer

Freescale Semiconductor - NXP

Part Status

Active

Series

MPC83xx

Package

369-LFBGA

Packaging

Tray

Family Name

PowerQUICC II Pro

Address Bus Width

0.0

Bit Size

32

Boundary Scan

Yes

Core

e300c3

Core Processor

PowerPC e300c3

Co Processors DSP

Communications; QUICC Engine

Clock Frequency Max

66.67 MHz

Device Core

e300

Data Bus Width

32 bit

Data Cache Size

16 KB

Display & Interface Controllers

-

Ethernet

3

Ethernet Speed

10 Mbps/100 Mbps

Ethernet Interface Type

MII/RMII

External Data Bus Width

0.0

Format

FLOATING POINT

Graphics Acceleration

No

I-O-Voltage

1.8 V, 3.3 V

Interface Type

CAN/Ethernet/I2C/SPI/UART/USB

Instruction Type

Floating Point

Integrated Cache

Yes

Instruction Cache Size

16 KB

Instruction Set Architecture

RISC

JESD-30 Code

S-PBGA-B369

JESD-609 Code

e2

Low Power Mode

Yes

L1-Cache-Instruction-Memory

16 kB

L1-Cache-Data-Memory

16 kB

Memory Type

L1 Cache

Mounting

Surface Mount

Mountingstyle

SMD/SMT

Multiply Accumulate

No

Moisture Sensitivity Level

3

Maximum CPU Frequency

333 MHz

Typical Operating Supply Voltage

3.3 V

Minimum Operating Supply Voltage

3 V

Maximum Operating Supply Voltage

3.6 V

Number of Cores

1 Core

Number of Terminals

369

Number of CPU Cores

1

Number of Cores Bus Width

1 Core, 32-Bit

Operating Supply Voltage

1 V

Operating Temperature Min

- 40 °C

Operating Temperature Max

105.0 °C

Pin Count

369

PCB changed

369

Processor Series

PowerQUICC II Pro

Package Case

MAPBGA-369

Package Body Material

PLASTIC/EPOXY

Package Code

LFBGA

Package Shape

SQUARE

Package Style

GRID ARRAY, LOW PROFILE, FINE PITCH

Peak Reflow Temperature

260 °C

RAM Controllers

DDR2

Speed

333MHz

Security Features

-

Supply Voltage Nom

1.0 V

Supply Voltage Min

0.95 V

Supply Voltage Max

1.05 V

Seated Height Max

1.61 mm

Supplier Package

MAP-BGA

Supplier Device Package

369-PBGA (19x19)

Standard Package Name

BGA

Surface Mount

Yes

Technology

CMOS

Tradename

PowerQUICC

Terminal Finish

TIN COPPER/TIN SILVER

Terminal Form

BALL

Terminal Pitch

0.8 mm

Terminal Position

BOTTOM

RoHS Compliant

Yes

Voltage-I-O

1.8V, 3.3V

Length

19.0 mm

Width

19.0 mm

Lead Shape

BALL

Lead Free Status

Lead free

ECCN

3A991.a.2

I2C

1

I2S

0

CAN

4

SPI

1

USB

USB 2.0 (1)

UART

3

SATA

-

USART

0

Unit-Weight

0.036516 oz

MPC8306SCVMAFDCA Datasheet PDF Download:

MPC8306SCVMAFDCA Datasheet PDF 

Description

The MPC8306S incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8306S also includes two DMA engines and a 16-bit DDR2 memory controller.

A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8306S. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure.

MPC8306S Block Diagram

Fig 1. Block Diagram

Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII Ethernet, HDLC and TDM.

In summary, the MPC8306S provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements.

Features

• High-performance M68HC08 CPU core

e300c3 Power Architecture processor core

Enhanced version of the MPC603e core

High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times

Floating-point, dual integer units, load/store, system register, and branch processing units

16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities

Dynamic power management

Enhanced hardware program debug features

Software-compatible with Freescale processor families implementing Power Architecture technology

Separate PLL that is clocked by the system bus clock

Performance monitor

QUICC Engine block

32-bit RISC controller for flexible support of the communications peripherals with the following features:

One clock per instruction

Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization

32-bit instruction object code

Executes code from internal IRAM

32-bit arithmetic logic unit (ALU) data path

Modular architecture allowing for easy functional enhancements

Slave bus for CPU access of registers and multiuser RAM space

48 Kbytes of instruction RAM

16 Kbytes of multiuser data RAM

Serial DMA channel for receive and transmit on all serial channels

Five unified communication controllers (UCCs) supporting the following protocols and interfaces:

10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.

HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)

HDLC Bus (bit rate up to 10 Mbps)

Asynchronous HDLC (bit rate up to 2 Mbps)

Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps

For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference Manual with Protocol Interworking.

DDR SDRAM memory controller

Programmable timing supporting DDR2 SDRAM

Integrated SDRAM clock generation

16-bit data interface, up to 266-MHz data rate

14 address lines

The following SDRAM configurations are supported:

Up to two physical banks (chip selects), 256-Mbyte per chip select for 16 bit data interface.

64-Mbit to 2-Gbit devices with x8/x16 data ports (no direct x4 support)

One 16-bit device or two 8-bit devices on a 16-bit bus,

Support for up to 16 simultaneous open pages for DDR2

One clock pair to support up to 4 DRAM devices

Supports auto refresh

On-the-fly power management using CKE

Enhanced local bus controller (eLBC)

Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz

Eight chip selects supporting eight external slaves

Four chip selects dedicated

Four chip selects offered as multiplexed option

Supports boot from parallel NOR Flash and parallel NAND Flash

Supports programmable clock ratio dividers

Up to eight-beat burst transfers

16- and 8-bit ports, separate LWE for each 8 bit

Three protocol engines available on a per chip select basis:

General-purpose chip select machine (GPCM)

Three user programmable machines (UPMs)

NAND Flash control machine (FCM)

Variable memory block sizes for FCM, GPCM, and UPM mode

Default boot ROM chip select with configurable bus width (8 or 16)

Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC slave devices

Integrated programmable interrupt controller (IPIC)

Functional and programming compatibility with the MPC8260 interrupt controller

Support for external and internal discrete interrupt sources

Programmable highest priority request

Six groups of interrupts with programmable priority

External and internal interrupts directed to host processor

Unique vector number for each interrupt source

Universal serial bus (USB) dual-role controller

Designed to comply with Universal Serial Bus Revision 2.0 Specification

Supports operation as a stand-alone USB host controller

Supports operation as a stand-alone USB device

Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.

Low speed is only supported in host mode.

Dual I2C interfaces

Two-wire interface

Multiple-master support

Master or slave I2

C mode support

On-chip digital filtering rejects spikes on the bus

I2

C1 can be used as the boot sequencer

DMA Engine

Support for the DMA engine with the following features:

Sixteen DMA channels

All data movement via dual-address transfers: read from source, write to destination

Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations

Channel activation via one of two methods (for both the methods, one activation per execution of the minor loop is required):

Explicit software initiation

Initiation via a channel-to-channel linking mechanism for continuous transfers (independent channel linking at end of minor loop and/or major loop)

Support for fixed-priority and round-robin channel arbitration

Channel completion reported via optional interrupt requests

Support for scatter/gather DMA processing

DUART

Two 2-wire interfaces (RxD, TxD)

The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)

Programming model compatible with the original 16450 UART and the PC16550D

Serial peripheral interface (SPI)

Master or slave support

Power managemnt controller (PMC)

Supports core doze/nap/sleep/ power management

Exits low power state and returns to full-on mode when

The core internal time base unit invokes a request to exit low power state

aracteristics

The power management controller detects that the system is not idle and there are outstanding transactions on the internal bus or an external interrupt.

Parallel I/O

General-purpose I/O (GPIO)

56 parallel I/O pins multiplexed on various chip interfaces

Interrupt capability

System timers

Periodic interrupt timer

Software watchdog timer

Eight general-purpose timers

Real time clock (RTC) module

Maintains a one-second count, unique over a period of thousands of years

Two possible clock sources:

External RTC clock (RTC_PIT_CLK)

CSB bus clock

IEEE Std. 1149.1™ compliant JTAG boundary scan

Other data sheets within the file:

Datasheet

MPC8306S Datasheet

MPC8306S Datasheet

MPC8306(S) Fact Sheet

MPC8306(S) Fact Sheet


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