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Dec 6 2019

MPC8280CZUUPEA Datasheet PDF - IC MPU MPC82XX 450MHZ 480TBGA NXP

Product Overview

Product Category:

Embedded - Microprocessors

Kynix Part #:

KY32-MPC8280CZUUPEA

Manufacturer Part#:

MPC8280CZUUPEA

Manufacturer

Freescale Semiconductor - NXP

Description:

IC MPU MPC82XX 450MHZ 408TBGA

Package:

480-LBGA

Datasheet:

MPC8280CZUUPEA Datasheet

Stock:

Yes

Quantity:

1183 PCS


MPC8280CZUUPEA Images are for reference only:

 MPC8280CZUUPEA Image

Product Specifications 

Categories

Integrated Circuits (ICs) Embedded - Microprocessors

Manufacturer

NXP USA Inc.

Series

MPC82xx

Packaging

Tray

Part Status

Active

Core Processor

PowerPC G2_LE

Number of Cores/Bus Width

1 Core, 32-Bit

Speed

450MHz

Co-Processors/DSP

Communications; RISC CPM

RAM Controllers

DRAM, SDRAM

Graphics Acceleration

No

Display & Interface Controllers

-

Ethernet

10/100Mbps (3)

SATA

-

USB

USB 2.0 (1)

Voltage - I/O

3.3V

Operating Temperature

-40°C ~ 105°C (TA)

Security Features

-

Package / Case

480-LBGA Exposed Pad

Supplier Device Package

480-TBGA (37.5x37.5)

Additional Interfaces

I²C, SCC, SMC, SPI, UART, USART

Base Part Number

MPC8280

Mfr Package Description

37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480

Status

Transferred

Address Bus Width

32.0

Bit Size

32

Boundary Scan

YES

Clock Frequency-Max

100.0  MHz

External Data Bus Width

64.0

Format

FLOATING POINT

Integrated Cache

YES

JESD-30 Code

S-PBGA-B480

JESD-609 Code

e0

Low Power Mode

NO

Moisture Sensitivity Level

4

Number of Terminals

480

Operating Temperature-Min

0.0  Cel

Operating Temperature-Max

70.0  Cel

Package Body Material

PLASTIC/EPOXY

Package Code

LBGA

Package Equivalence Code

BGA480,29X29,50

Package Shape

SQUARE

Package Style

GRID ARRAY, LOW PROFILE

Peak Reflow Temperature (Cel)

260

Power Supplies

1.5,3.3

Qualification Status

Not Qualified

Seated Height-Max

1.65  mm

Speed

450.0  MHz

Sub Category

Other uPs/uCs/Peripheral ICs

Supply Voltage-Nom

1.5  V

Supply Voltage-Min

1.45  V

Supply Voltage-Max

1.6  V

Surface Mount

YES

Technology

CMOS

Temperature Grade

COMMERCIAL

Terminal Finish

TIN LEAD

Terminal Form

BALL

Terminal Pitch

1.27  mm

Terminal Position

BOTTOM

Time@Peak Reflow Temperature-Max (s)

40

Length

37.5  mm

Width

37.5  mm

Additional Feature

ALSO REQUIRES 3.3V SUPPLY


MPC8280CZUUPEA Datasheet PDF Download:

 MPC8280CZUUPEA Datasheet PDF

Block Diagram

Fig 1. SoC Block Diagram 

Fig 1. SoC Block Diagram

Pin Assignments

Fig 2. Pinout of the 480 TBGA Package (View from Top) 

 Fig 2. Pinout of the 480 TBGA Package (View from Top)

 Fig 3. Pinout of the 516 PBGA Package (View from Top)

 Fig 3. Pinout of the 516 PBGA Package (View from Top)

 

Description

There is no relevant information available for this part yet.

Features

The major features of the SoC are as follows:

• Dual-issue integer (G2_LE) core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 166–450 MHz

— Separate 16 KB data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— Power Architecture®-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz)

— Supports bus snooping

— Support for data cache coherency

— Floating-point unit (FPU)

• Separate power supply for internal logic and for I/O

• Separate PLLs for G2_LE core and for the communications processor module (CPM)

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1

— Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios

• 64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

• 32-bit data and 18-bit address local bus

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

• 60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

• PCI bridge

— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming

— PCI host bridge or peripheral capabilities

— Includes 4 DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

— Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8280) required by the PCI standard as well as message and doorbell registers

— Supports the I2O standard

— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August 3, 1998)

— Support for 66.67/83.33/100 MHz, 3.3 V specification

— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port

— Uses the local bus signals, removing need for additional pins

• System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

• 12-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other user-definable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page mode pipeline SDRAM machine

— Byte selects for 64-bit bus width (60x) and byte selects for 32-bus width (local)

— Dedicated interface logic for SDRAM

• CPU core can be disabled and the device can be used in slave mode to an external core

• Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols

— Interfaces to G2_LE core through an on-chip 32 KB dual-port data RAM, an on-chip 32 KB dual-port instruction RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols:

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) or reduced media independent interface (RMII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external connections (no ATM support for the MPC8270)

– Transparent

– HDLC—Up to T3 rates (clear channel)

– FCC2 can also be connected to the TC layer (MPC8280 only)

— Two multichannel controllers (MCCs) (one MCC on the MPC8270)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC

— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BISYNC) communications

– Transparent

• Universal serial bus (USB) controller

— Supports USB 2.0 full/low rate compatible

— USB host mode

– Supports control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stuffing

– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub.

– Flexible data buffers with multiple buffers per frame

– Supports local loopback mode for diagnostics (12 Mbps only)

— Supports USB slave mode

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

– Flexible data buffers with multiple buffers per frame

– Automatic retransmission upon transmit error

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provides management for BRI devices as general-circuit interface (GCI) controllers in time-division-multiplexed (TDM) channels

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

— One I2 C controller (identical to the MPC860 I2C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to eight TDM interfaces (four on the MPC8270)

– Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270 and the MPC8275)

– 2,048 bytes of SI RAM

– Bit or byte resolution

– Independent transmit and receive routing, frame synchronization

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

• Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only). Supported by eight transfer transmission convergence (TC) layers between the TDMs and FCC2.

• Transmission convergence (TC) layer (MPC8280 only)

Other data sheets within the file:

Datasheets

MPC8280 PowerQUICC II Family

MPC8280 PowerQUICC II Family

NXP RoHS3 Cert

NXP RoHS3 Cert

Development Tool Selector

Development Tool Selector

PCN Design/Specification

Copper Bond Wire Qualification 07/Sep/2014

Copper Bond Wire Qualification 07/Sep/2014

Trace Marking Removal 20/Jun/2019

Trace Marking Removal 20/Jun/2019

MPC82xx

MPC82xx

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