MPC8275VRMIBA Datasheet PDF - IC MPU MPC82XX NXP FREESCALE

Product Overview

MPC8275VRMIBA Images are for reference only:

Product Specifications 

MPC8275VRMIBA Datasheet PDF Download:

Block Diagram

Fig. 1 SoC Block Diagram

Notes:

1 MPC8280 only (not on MPC8270, the VR package, nor the ZQ package)

2 MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have only 1 SI block and 4 TDM ports (TDM2[A–D]).

3 MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)

Description

Introducing the next generation of PowerQUICC II processors: the MPC8270, MPC8275 and MPC8280. Utilizing Freescale's HiPerMOS7 0.13-micron process technology, the next generation PowerQUICC II family offers a range of performance, feature enhancements and package options with lower power requirements. Ideal for wired and wireless infrastructure communications processing tasks, enhancements to the PowerQUICC II family offer system designers a high degree of integrated features and functionality and a compelling, proven architecture. The next generation of PowerQUICC II processors is an optimum solution for integrated control and forwarding plane processing in high-end communications and networking equipment -- such as routers, DSLAMs, remote access concentrators, telecom switching equipment and cellular base stations. Combining extensive layer 2 functionality with control plane processing, Freescale's PowerQUICC II processors include a high-performance embedded 603e core built on Power Architecture technology and a powerful RISC-based Communications Processor Module (CPM). The CPM off-loads peripheral tasks from the embedded core and provides support for multiple communications protocols, including 10/100Mbps Ethernet, 155Mbps ATM and 256 HDLC channels. And, of course, the next generation PowerQUICC II devices retain full software compatibility with the PowerQUICC II family. A range of performance and package options Taking advantage of the 0.13-micron process, the next generation of PowerQUICC II devices offers significant performance increases and power savings over the current generation PowerQUICC II devices, with speeds of up to 450MHz and 300MHz in the core and CPM respectively at less than 2 watts. The new processors continue to enhance the PowerQUICC architecture's industry-leading ATM support, offering up to 2 UTOPIA ports with support for up to 31 PHYs per interface -- ideal for high-density DSLAM line cards. The next generation of PowerQUICC II solutions also delivers support for USB, an on-target addition for high performance SOHO and CPE networking equipment. And unlike most other integrated communications processors in the market, the PowerQUICC architecture integrates two processing cores to handle specific tasks: the core built on Power Architecture technology and the RISC-based CPM -- enabling a balanced approach for systems by handling both high-level tasks and low-level communications all in one integrated device.

Features

• 603e core with 16K inst and 16K data caches

• 64-bit 60x bus, 32-bit Local / PCI bus

• 128K ROM, 32K IRAM, 32K DPRAM

• Three FCCs supporting ATM, 10/100 Ethernet or HDLC (no IMA/TC support)

• 128 HDLC channels, 4 TDMs

• 4 SCCs, 2 SMCs, SPI, I2C

• Memory controller built from SDRAM, UPM, GPCM machines

• New features -- USB, RMII, UTOPIA improvements

• Performance

266 MHz CPU, 200 MHz CPM, 66 MHz bus

~1W @ full performance, 1.5V

• Technology

HIP7AP .13 micron, 3.3V I/O, 1.5V Core

516 PBGA, 27x27mm, 1mm ball pitch

ZQ package has lead-bearing spheres

VR package is lead-free

Other data sheets within the file:

Datasheets
MPC8280 PowerQUICC II Family
Application Notes
CPM Architecture and Downloading RAM Microcodes on the PowerQUICC II Family
CPM/CPU Interaction
Differences Among PowerQUICC II Devices and Revisions
Interfacing SDRAM Devices to the PowerQUICC MPC8280 at 100 MHz
MPC8260 Reset and Configuration Word
MPC8260 SDRAM Support
MPC82xx PowerQUICC II Reset Sources and Effects
Test/Quality Data
Material Composition
RoHS Certificate of Analysis
Statement on EU REACH Provisions