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Apr 25 2019

MC912D60AMFUE8 Datasheet PDF - IC MCU 16BIT 60KB FLASH 80QFP FREESCALE

Product Overview

Product Category:

Embedded - Microcontrollers

Kynix Part #:

KY32-MC912D60AMFUE8

Manufacturer Part#:

MC912D60AMFUE8

Manufacturer

NXP USA Inc.

Description:

IC MCU 16BIT 60KB FLASH 80QFP

Package:

80-QFP

Datasheet:

MC912D60AMFUE8 Datasheet

Stock:

Yes

Quantity:

955 PCS


MC912D60AMFUE8 Images are for reference only:

MC912D60AMFUE8 Image

Product Specifications 

Categories

Integrated Circuits (ICs)

Embedded - Microcontrollers

Series

HC12

Core Processor

CPU12

Core Size

16-Bit

Connectivity  

CANbus, MI Bus, SCI, SPI

Speed

8MHz

Data Bus Width

16 Bit

Data Converters

A/D 8x8/10b

EEPROM Size

1K x 8

Instruction Set Architecture

CISC

Height

2.4 mm

Length

14 mm

Width

14 mm

Lead Finish

Matte Tin

Max Processing Temp

260 °C

Maximum Expanded Memory Size

64 KB

Maximum Operating Supply Voltage

5.5 V

Maximum Speed

8 MHz

Minimum Operating Supply Voltage

4.5 V

Mounting  

Surface Mount

Number of Programmable I/Os

58

Oscillator Type 

Internal

On-Chip ADC 

8-chx10-bit

Operating Supply Voltage

5 V

Operating Temperature

-40 to 125 °C

Pin Count

80

Product Dimensions

14 x 14 x 2.4 mm

Program Memory Size

60KB (60K x 8)

Packaging

Tray

Part Status

Not For New Designs

Peripherals

POR, PWM, WDT

Program Memory Type

FLASH

Package / Case

80-QFP

Product Type

16-bit Microcontrollers - MCU

Supplier Device Package

80-QFP (14x14)

RAM Size

2K x 8

Supplier Package

PQFP

Voltage - Supply (Vcc/Vdd)

4.5V ~ 5.5V

Watchdog

1

Subcategory

Microcontrollers - MCU

Base Part Number

MC912D60

Brand

NXP / Freescale

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Moisture Sensitivity Level (MSL)

3 (168 Hours)


MC912D60AMFUE8 Datasheet PDF Download:

MC912D60AMFUE8 Datasheet PDF

Block Diagrams

MC68HC912D60A 112-pin QFP Block Diagram

Fig. 1 MC68HC912D60A 112-pin QFP Block Diagram

MC68HC912D60A 80-pin QFP Block Diagram

Note: 

Several I/O on ports G, H and CAN are unavailable externally on the 80-pin QFP package. 

These internal pins should either be defined as outputs or have their pull-ups/downs enabled.

Fig. 2 MC68HC912D60A 80-pin QFP Block Diagram


Pin Assignments

Pin Assignments in 112-pin TQFP for MC68HC912D60A

Note: 

TEST = This pin is used for factory test purposes. 

It is recommended that this pin is not connected in the application, but it may be bonded to 5.5 V max without issue.

Never apply voltage higher than 5.5 V to this pin.

Fig. 3 Pin Assignments in 112-pin TQFP for MC68HC912D60A

Pin Assignments in 80-pin QFP for MC68HC912D60A


Note: 

TEST = This pin is used for factory test purposes. 

It is recommended that this pin is notconnected in the application, but it may be bonded to 5.5 V max without issue.

Never apply voltage higher than 5.5 V to this pin.

Fig. 4 Pin Assignments in 80-pin QFP for MC68HC912D60A

Description

The 68HC912D60A microcontroller unit (MCU) is a 16-bit device available in two package options, 80-pin QFP and 112-pin TQFP. On-chip peripherals include a 16-bit central processing unit (CPU12), 60K bytes of flash EEPROM, 2K bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communication interfaces (SCI), a serial peripheral interface (SPI), an enhanced capture timer (ECT), two (one on 80QFP) 8-channel, 10-bit analog-to-digital converters (ATD), a four-channel pulse-width modulator (PWM), and a CAN 2.0 A, B software compatible module (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the lite integration module (LIM). The 68HC912D60A has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 16 (2 on 80QFP) I/O port pins are available with Key-Wake-Up capability from STOP or WAIT mode.

Features

• 16-bit CPU12

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to M68HC11

– 20-bit ALU

– Instruction queue

– Enhanced indexed addressing

• Multiplexed bus

– Single chip or expanded

– 16 address/16 data wide or 16 address/8 data narrow mode

• Two 8-bit ports with key wake-up interrupt (2 pins only are available on 80QFP) and one I2C start bit detector (112TQFP only)

• Memory

– 60K byte flash EEPROM, made of a 28K module and a 32K module with 8K bytes protected BOOT section in each module (MC68HC912D60A)

– 1K byte EEPROM

– 2K byte RAM

• Analog-to-digital converters

– 2 x 8-channels, 10-bit resolution in 112TQFP

– 1 x 8-channels, 8-bit resolution in 80QFP

• 1M bit per second, CAN 2.0 A, B software compatible module

– Two receive and three transmit buffers

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

– Low-pass filter wake-up function

– In 80QFP, only TxCAN and RxCAN pins are available

– Loop-back for self test operation

– Programmable link to a timer input capture channel, for timestamping and network synchronization.

• Enhanced capture timer (ECT)

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer

– Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four

– Four 8-bit or two 16-bit pulse accumulators

– 16-bit modulus down-counter with 4-bit prescaler

– Four user-selectable delay counters for signal filtering

• 4 PWM channels with programmable period and duty cycle

– 8-bit 4-channel or 16-bit 2-channel

– Separate control for each pulse width and duty cycle

– Center- or left-aligned outputs

– Programmable clock select logic with a wide range of frequencies

• Serial interfaces

– Two asynchronous serial communications interfaces (SCI)

– MI-Bus implemented on final devices

– Synchronous serial peripheral interface (SPI)

• LIM (light integration module)

– WCR (windowed COP watchdog, real time interrupt, clock monitor)

– ROC (reset and clocks)

– MEBI (multiplexed external bus interface)

– MBI (internal bus interface and map)

– INT (interrupt control)

• Clock generation

– Phase-locked loop clock frequency multiplier

– Limp home mode in absence of external clock

– Slow mode divider

– Low power 0.5 to 16 MHz crystal oscillator reference clock

– Option of a Pierce or Colpitts oscillator

• 112-Pin TQFP package or 80-pin QFP package

– Up to 68 general-purpose I/O lines, plus up to 18 input-only lines in 112TQFP Or Up to 48 general-purpose I/O lines, plus up to 10 input-only lines in 80QFP

• 8MHz operation at 5V

• Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

Other data sheets within the file:

Datasheet

MC68HC912D60C, MC68HC912D60P Technical DataSheet

MC68HC912D60C, MC68HC912D60P Technical DataSheet

Application Notes

Designing for Board Level Electromagnetic Compatibility (REV 1)

Designing for Board Level Electromagnetic Compatibility (REV 1)

Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers

Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers

Liquid Level Control Using a Pressure Sensor

Liquid Level Control Using a Pressure Sensor

Noise Reduction Techniques for Microcontroller-Based Systems

Noise Reduction Techniques for Microcontroller-Based Systems

System Design and Layout Techniques for Noise Reduction in MCU-Based Systems

System Design and Layout Techniques for Noise Reduction in MCU-Based Systems

FLASH Programming Via CAN (REV 1)

FLASH Programming Via CAN (REV 1)

Compatibility considerations between the 0.65u ROM M68HC12D60 and the 0.5u Flash M68HC912D60A (REV 0)

Compatibility considerations between the 0.65u ROM M68HC12D60 and the 0.5u Flash M68HC912D60A (REV 0)

Programming and Erasing FLASH and EEPROM Memories on the MC68HC912DT128A/DG128A/D60A (REV 0)

Programming and Erasing FLASH and EEPROM Memories on the MC68HC912DT128A/DG128A/D60A (REV 0)

Transporting M68HC11 Code to M68HC12 Devices

Transporting M68HC11 Code to M68HC12 Devices

Using M68HC12 Indexed Indirect Addressing

Using M68HC12 Indexed Indirect Addressing

Using the Callable Routines in D-Bug12

Using the Callable Routines in D-Bug12

PCN

Copper Wire Conversion for Microcontroller and Microprocessor Devices

Copper Wire Conversion for Microcontroller and Microprocessor Devices

Technical Resources

Use of OSC2/XTAL as a Clock Output on Motorola Microcontrollers

Use of OSC2/XTAL as a Clock Output on Motorola Microcontrollers

Test/Quality Data

Material Composition

Material Composition

RoHS Certificate of Analysis

RoHS Certificate of Analysis

Statement on EU REACH Provisions

Statement on EU REACH Provisions

Reference Manual

CPU12 - Reference Manual (REV 4)

CPU12 - Reference Manual (REV 4)

CPU12 Reference Guide (REV 2)

CPU12 Reference Guide (REV 2)



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