MC68LC302PU20CT Datasheet PDF - IC M68000 MPU M683XX 20MHZ 100LQFP

Product Overview

MC68LC302PU20CT Images are for reference only:

Product Specifications 

MC68LC302PU20CT Datasheet PDF Download: 

Pin Assignments

Fig. 1 MC68LC302 Pin Description

Description

The MC68LC302 excels in several applications areas.

First, any application using the MC68302,but not needing all three serial channels is a potential candidate for the MC68LC302. Note however, that the MC68LC302 sacrifices most of the provision for external bus mastership, thus the MC68LC302 may not be appropriate where the MC68302 is used as part of larger systems.

Second, the MC68LC302 excels in low power and portable applications. The inclusion of a static 68000 core, coupled with the low power modes built into the device make it ideal for handheld, or other low power applications. The new 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer’s board, and allows the MC68LC302 to be an effective device in low power systems. The MC68LC302 can then optionally generate a full frequency clock for use by the rest of the board. During low power modes, the new periodic interrupt timer (PIT) allows the device to awaken at regular intervals. In addition, two pins can awaken the device from low power modes.

Third, given that the MC68LC302 is packaged in a 100TQFP package, it allows the MC68LC302 to be used in space critical applications, as well as height critical applications such as PCMCIA cards.

Fourth, since the disable CPU mode (also known as slave mode) is still retained, the MC68LC302 can function as a fully intelligent DMA-driven peripheral chip containing serial channels, timers, chip selects, etc.

Features

• On-Chip Static 68000 Core Supporting a 16- or 8-Bit M68000 Family System

• SIB Including:

— Independent Direct Memory Access (IDMA) Controller

— Interrupt Controller with Two Modes of Operation

— Parallel Input/Output (I/O) Ports, Some with Interrupt Capability

— On-Chip 1152-Byte Dual-Port RAM

— Three Timers Including a Watchdog Timer

— New Periodic Interrupt Timer (PIT)

— Four Programmable Chip-Select Lines with Wait-State Generator Logic

— Programmable Address Mapping of the Dual-Port RAM and IMP Registers

— On-Chip Clock Generator with Output Signal

— On-Chip PLL Allows Operation with 32 kHz or 4 MHz Crystals

— Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM

— Allows Boot in 8-bit Mode, and Running Switch to 16-bit Mode

— System Control:

     System Status and Control Logic

    Disable CPU Logic (Slave Mode Operation)

    Hardware Watchdog

    New Low-Power (Standby) Modes with Wake-Up from Two Pins or PIT

    Freeze Control for Debugging (Available Only in the PGA Package)

    DRAM Refresh Controller

• CP Including:

— Main Controller (RISC Processor)

— Two Independent Full-Duplex Serial Communications Controllers (SCCs)

— Supporting Various Protocols:

    High-Level/Synchronous Data Link Control (HDLC/SDLC)

    Universal Asynchronous Receiver Transmitter (UART)

    Binary Synchronous Communication (BISYNC)

    Transparent Modes

    Autobaud Support 

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