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Mar 27 2019

MC68360CVR25L Datasheet PDF - IC MPU M683XX 25MHZ 357BGA

Product Overview

Product Category:Embedded - Microprocessors
Kynix Part #:KY32-MC68360CVR25L
Manufacturer Part#:MC68360CVR25L
Manufacturer:Freescale Semiconductor, Inc.
Description:MPU ColdFire M683xx Processor RISC 32bit 0.57um 25MHz 240-Pin FQFP Tray
Package:357-BBGA
Datasheet:MC68360CVR25L Datasheet
Stock:Yes
Quantity:112PCS



MC68360CVR25L Images are for reference only:

MC68360CVR25L

Product Specifications

Categories

Integrated Circuits (ICs)

Embedded - Microprocessors

SeriesM683xx
Core ProcessorCPU32+
Co-Processors/DSPCommunications; CPM
Device Core   ColdFire
Data Bus Width (bit)  32
Display & Interface Controllers0
Ethernet10 Mbps (1)
Graphics AccelerationNo
Voltage - I/O (V)5.0
Operating Temperature-40°C ~ 85°C (TA)
Additional InterfacesSCC, SMC, SPI
Base Part NumberMC68360
EU RoHS   Compliant
ECCN (US)  3A991.a.2
HTS   8542.31.00.01
Family Name  ColdFire M683xx Processor
Instruction Set Architecture    RISC
Interface Type   SPI/UART
UART1
USART0
USB0
SPI 1
I2C0
I2S0
CAN0
Ethernet0
SATA-
Maximum Speed (MHz)25
Minimum Operating Supply Voltage (V)4.75
Maximum Operating Supply Voltage (V)5.25
Minimum Operating Temperature (°C) -40
Maximum Operating Temperature (°C)85
Mounting     Surface Mount
Multiply Accumulate  No
Number of CPU Cores1
On-Chip Memory2.5KB/RAM
Part Status  NRND
Packaging  Tray
Pin Count  240
Package / Case357-BBGA
Part StatusNot For New Designs
Package Height   3.5(Max)
Package Length   32
Package Width32
PCB changed   240240
RAM ControllersDRAM
Security Features-
Supplier Package  FQFP
Standard Package Name  QFP
Supplier Device Package357-PBGA (25x25)
Typical Operating Supply Voltage (V)5



MC68360CVR25L Datasheet PDF Download:

MC68360CVR25L

Pinouts:

PIN ASSIGNMENT—240-LEAD QUAD FLAT PACK (QFP)

PIN ASSIGNMENT—240-LEAD QUAD FLAT PACK (QFP) 1.jpgPIN ASSIGNMENT—240-LEAD QUAD FLAT PACK (QFP) 2.jpg

PIN ASSIGNMENT—241-LEAD PIN GRID ARRAY (PGA)

PIN ASSIGNMENT—241-LEAD PIN GRID ARRAY (PGA).jpg

PIN ASSIGNMENT—357-LEAD BALL GRID ARRAY (BGA)

PIN ASSIGNMENT—357-LEAD BALL GRID ARRAY (BGA).jpg

Description

The MC68360 Quad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated microprocessor and peripheral combination family that can be used in a variety of controller applications.

The MC68360 particularly excels in communications activities. The QUICC can be described as a next-generation MC68302, with higher performance in all areas of device operation, increased flexibility, and higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device. However, there are actually seven serial channels which include four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).

Features

•  CPU32+ Processor (4.5 MIPS at 25 MHz)

—   32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)

—   Background Debug Mode

—   Byte-Misaligned Addressing

•   Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)

•   Up to 32 Address Lines (At Least 28 Always Available)

•   Complete Static Design (0–25-MHz Operation)

•   Slave Mode To Disable CPU32+ (Allows Use with External Processors)

—   Multiple QUICCs Can Share One System Bus (One Master)

—   MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion Memory (SRAM), Electrically Programmable Read-Only Memory (EPROM), Flash EPROM, etc

—   Four CAS lines, Four WE lines, One OE line

—   Boot Chip Select Available at Reset (Options for 8-, 16-, or 32-Bit Memory)

•   Four General-Purpose Timers

—   Superset of MC68302 Timers

—   Four 16-Bit Timers or Two 32-Bit Timers

—   Gate Mode Can Enable/Disable Counting

•   Two Independent DMAs (IDMAs)

—   Single Address Mode for Fastest Transfers

—   Buffer Chaining and Auto Buffer Modes

—   Automatically Performs Efficient Packing

—   32-Bit Internal and External Transfers

•   System Integration Module (SIM60)

—   Bus Monitor

—   Double Bus Fault Monitor

—   Spurious Interrupt Monitor

—   Software Watchdog

—   Periodic Interrupt Timer

—   Low Power Stop Mode

—   Clock Synthesizer

—   Breakpoint Logic Provides On-Chip Hardware Breakpoints

—   External Masters May Use On-Chip Features Such As Chip Selects

—   On-Chip Bus Arbitration with No Overhead for Internal Masters

—   IEEE 1149.1 Test Access Port

•   Interrupts

—   Seven External IRQ Lines

—   12 Port Pins with Interrupt Capability

—   16 Internal Interrupt Sources

—   Programmable Priority Between SCCs

—   Programmable Highest Priority Request

•   Communications Processor Module (CPM)

—   RISC Controller

—   Many New Commands (e.g., Graceful Stop Transmit, Close RxBD)

—   224 Buffer Descriptors

—   Supports Continuous Mode Transmission and Reception on All Serial Channels

•   Four SCCs

—   Ethernet/IEEE 802.3 Optional on SCC1 (Full 10-Mbps Support) (Available only on theMC68EN360)

—   HDLC/SDLC™(All Four Channels Supported at 2 Mbps)

—   HDLC Bus (Implements an HDLC-Based Local Area Network (LAN))

—   AppleTalk®

—   Signaling System #7

—   Universal Asynchronous Receiver Transmitter (UART)

—   Synchronous UART

—   Binary Synchronous Communication (BISYNC)

—   Totally Transparent (Bit Streams)

—   Totally Transparent (Frame Based with Optional Cyclic Redundancy Check (CRC))

—   Profibus (RAM Microcode Option)

—   Asynchronous HDLC (RAM Microcode Option) to Support PPP (Point to Point Protocol)

—   DDCMP™(RAM Microcode Option)

—   V.14 (RAM Microcode Option)

—   X.21 (RAM Microcode Option)

•   Two SMCs

—   UART

—   Transparent

—   General Circuit Interface (GCI) Controller

—   Can Be Connected to the Time-Division Multiplexed (TDM) Channels

•   One SPI

—   Superset of the MC68302 SCP

—   Supports Master and Slave Modes

—   SupportsMultimaster Operation on the Same Bus

•   Time-Slot Assigner

•   Supports Two TDM Channels

—   Each TDM Channel Can Be T1, CEPT, PCM Highway, ISDN Basic Rate,ISDN Primary Rate, User Defined

—   1- or 8-Bit Resolution

—   AllowsIndependent Transmit and Receive Routing, Frame Syncs, Clocking

—   AllowsDynamic Changes

—   Can Be internally Connected to Six Serial Channels (Four SCCs andTwo SMCs)

•   Parallel Interface Port (supports fast connection between QUICCs)

Other data sheets within the file:


MC68360CVR25L DatasheetMC68360CVR25L Datasheet
Product Change NotificationProduct Change Notification PDF
Customer Information NotificationCustomer Information Notification PDF
Material CompositionMaterial Composition PDF




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