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Aug 29 2019

FPGA And W3150A+ Have Been Choosen To Design The Ethernet Interface


Overall Design Of Ethernet Interface1. Choice Of Ethernet Interface Design Schema
2. Introduction Of Ethernet Control Chip W3150A+
IIIHardware Design Of Ethernet Interface1. Interface Design Of W3150A+ And FPGA
2. Interface Design Of The Physical Layer Chip And W3150A+
IVThe Realization Process Of Data Transmission


Virtual instrument quickly occupied the market with its advantages of high cost performance and strong openness, and became a new economic growth point of measurement and control instrument. The most significant sign of entering the information age is the penetration and popularization of information network in various industries, among which Ethernet is the most typical. Ethernet, as a network with low cost, strong throughput capacity, good adaptability and increasing network management ability, can easily integrate data acquisition system into LAN or even Internet. Ethernet bus may replace other bus methods and become the preferred interface of virtual instrument data acquisition system.

Overall Design Of Ethernet Interface

1. Choice Of Ethernet Interface Design Scheme

The design of Ethernet interface usually has three schemes: one is to use FPGA to realize the description of physical layer, network layer, access layer and transport layer, etc. This scheme’s difficult part is to realize the complex TCP /IP protocol by itself. The other one is based on the physical network controller and the microprocessor to implement the network transmission, the scheme has the advantage of strong flexibility which can realize agreement to streamline according to different system with a different protocol. The final way to achieve Ethernet data transmission is by a proprietary protocol processing chip, the hardware circuit of this scheme is relatively simple with short development cycle, and there are more and more chips to choose from, and a variety of protocols integrated, which make use convenient.

This design adopts the third interface scheme, that is, with the special TCP/IP protocol integrated chip, the control of the protocol processing chip realized by the FPGA, so as to implement the Ethernet data transmission. Protocol processing chip adopts W3150A+ which is internally solidified by TCP/IP protocol and is combined with physical layer chip RTL8201. The hardware circuit of this method is relatively simple and can be realized by logic hardware, thus making the system design more simple and compact.

2. Introduction Of Ethernet Control Chip W3150A+

W3150A+ is a TCP/IP stack chip developed by WIZnet specifically for Ethernet interconnection and embedded systems. W3150A+ can realize protocols such as TCP, UDP, IP ver.4, DHCP, ARP and ICMP. Meanwhile, the network interface layer (including MAC sub-layer and DLC sub-layer) can also be realized in this chip. At the same time, it can also provide a four-way network connection, and its internal 16KB dual-port RAM can be used as a data buffer, and can support full duplex mode, at the same time with the standard MD interface which make it can be easily connected to the physical layer interface chip. WIZnet also offers a Socket API package that speeds up application development.

  The structure diagram of W3150A+

Figure 1. The structure diagram of W3150A+

Figure 1 shows the structure block diagram of W3150A+ chip. As can be seen from figure 1, W3150A+ is mainly composed of four parts. The first part is the MCU interface. W3150A+ provides direct bus interface, indirect bus interface and SPI bus interface. It is not only suitable for connecting with the bus like 8051 single chip microcomputer, but also suitable for connecting with the controller with only IO port but no bus interface. The second part is the TCP /IP protocol stack. W3150A+ has completely solidified the protocols needed from MAC layer, network layer to transport layer. Therefore, users do not need to know the specific implementation methods and implementation codes of these protocols. The third part is the receive and send buffers through which data communicated over Ethernet is exchanged. The fourth part is Ethernet physical layer interface (MII interface). The W3150A + can be seamlessly connected to physical layer chip RTL8201 to achieve the 10/100baset Ethernet physical interface.

The internal registers of W3150A+ are divided into two storage and two types of registers. The two storage are used for the input and output of data transmission respectively. The two kinds of registers are general register and port register respectively. Each type of register contains a large number of state word control registers. The following is a brief introduction to the more important status word control register.

Sn_MR: Port n mode register, which is used to set the port's option or protocol type.

Sn_CR: Port n command register, which is used to set up port initialization, closure, connection establishment, disconnection, data transfer, and command acceptance, etc.

Sn_IR: Port n interrupt register, which is used to display information such as connection establishment and termination, data receipt, completion of transmission and time overflow, etc.

Sn_PORT: Port number register of port n, which can set the corresponding port number in TCP or UDP mode.

S_TX_FSR: Port n sending memory spare space register, which is used to indicate the size of the data space. Before sending data, the user must first check the size of the remaining space, and then control the number of bytes of data sent.

Sn_TX_RR: Port n sending memory read pointer register, which indicates the current location of the send memory after the send process is completed. When the command register of port n receives the SEND command, it can be immediately sent out from the current Sn_TX_RR to Sn_TX_WR data. After sending, the value of Sn_TX_RR will automatically change.

Sn_TX_WR: Port n transmission the write pointer register, which indicates the address at which data is written to the TX memory.

Sn_RX_RSR: Port n reception data bytes number register, which is just the number of bytes that the port receives the data buffer to receive the data. It is usually calculated from the value of Sn_TX_RR to Sn_TX_WR. After writing the RECV command to the port n command register, the value of the register will automatically change, and the remote opposite data can be received.

Sn_RX_RD: Port n reception buffer read pointer register, which is just read address information after the port receives process.

W3150A+ has four separate internal ports (Sockets) whose state and control are mapped in registers 2 through 5 respectively. It is mainly used to control the port working mode (TCP server, TCP client, UDP or PPPOE, etc.), set the port number of the port, set the IP address and port number of the port destination, and control the port to receive and send data.

Hardware Design Of Ethernet Interface

The hardware design of this interface mainly includes the interface design of FPGA and W3150A+, the interface design of physical chip RTL8201 and W3150A+, and the design of clock module and power module.

1. Interface Design Of W3150A+ And FPGA

With the rapid development of semiconductor technology, the computing power, capacity and reliability of FPGA (Field Programmable Gate Array) have been greatly improved. Thanks to the highly flexible user field programming function, repeatedly rewritable function, high reliability and other advantages, it has become the digital circuit, digital signal processing and other fields of the new favorite.

MAXII series of Altera company EPM570GT100C4 is the FPGA chip selected in this design considering cost, practicability and power consumption. MAXII is a non-volatile CPLD manufactured with a 0.18 micron process and with 240 to 2210 logic units and 8Kbits of non-volatile memory, providing a faster, more stable and larger number of I/O pins than other CPLDS.

W3150A+ has three interface modes with microprocessor chip: direct bus interface mode, indirect bus interface mode and SPI mode. The direct bus interface mode is suitable for large data transmission. SPI mode has few interface connections, which is suitable for the case of small data volume and relatively low transmission rate. The data transmission performance in the indirect bus interface mode is somewhere in between. The system adopts direct bus interface mode to maximize the data transmission rate.Its specific interface circuit is shown in figure 2.

the interface circuit diagram of the W3150A+ and FPGA 

Figure 2. the interface circuit diagram of the W3150A+ and FPGA

2. Interface Design Of The Physical Layer Chip And W3150A+

RTL8201BL is a single-port physical layer transceiver with a single MII/SNI (media independent interface/serial network interface) interface. It can be used to realize all physical layer functions of 10/100M Ethernet, including physical layer coding sub-layer (PCS), physical layer medium connection device (PMA), twisted pair physical media related sub-layer (TP ~ PMD), 10Base-Tx codec and twisted pair media access unit (TPMAU). The PECL interface supports connection to an external 100Base-Fx optical transceiver. The chip uses advanced CMOS technology to meet the needs of low voltage and low power consumption.

RTL8201BL and W3150A+ can be connected through the standard MII interface, where pins RX_CLK, RXDV, RXD [0:3] and COL are used for data reception, while TX_CLK, TXE and TXD [0:3] are used for data transmission. Its specific circuit diagram is shown in figure 3.

the interface circuit diagram of the physical layer chip and W3150A+ 

Figure 3. the interface circuit diagram of the physical layer chip and W3150A+

The Realization Process Of Data Transmission

W3150A+ can be connected to the network by read-write access to the register via the controller. The following describes the specific operation process.

Initialization should be performed first. Initialization Settings include basic Settings, network information Settings, port storage information Settings, etc. After setting, data transmission can be carried out. Data transmission can be done in TCP, UDP, IP_RAW and MAC_RAW modes, and communication mode can be selected from the protocol type of the port n mode register (Sn_MR). The basic Settings include the mode register (MR), interrupt mask register (SIMR), retransmit time register (RTR), retransmit count register (RGR), etc. Setting network information includes setting gateway (GAR), setting source hardware address (SHAR), setting SUBR, setting source IP address (SIPR), etc. While setting port storage information is mainly to set the size allocation of send buffer and receive buffer, which can be achieved by setting RMSR and TMSR registers.

Based on FPGA chip EPM570GT100C4, this system can use Quartus II software to develop logic control function, so as to realize the control of W3150A+. Its main ports are as follows:

NRST: reset input key, effective low level.

CLK: clock input.

NWRST: reset output, reset W3150A+ and RTL8201.

NWR: write enable signal to W3150A+, active at low level.

NRD: W3150A+ read enable signal, active at low levle.

NCS: W3150A+ chip selection signal, effective at low level.

Address: 15-bit address signal.

Data: 8-bit data signal.

The interface communication design adopts UDP communication mode, and its communication flow chart is shown in figure 4.

the flow chart of the design of the Ethernet interface 

Figure 4. the flow chart of the design of the Ethernet interface

Port initialization is mainly to initialize the port, including setting UDP mode, setting port number, setting OPEN command; The value of Sn_RX_RSR register can be used to detect whether the data is received or not. When receiving, first read the value of register Sn_RX_RSR, that is, the number of bytes of received data, then calculate the partial address and the actual physical address, and then read the data according to the physical address. In the process of reading data, if the physical address reaches the high-limit address set by the port, the data of the high-limit address is read first, then the physical address is changed to the base address, and then the remaining data is read from the base address. After reading all the data, add the value of Sn_RX_RR plus the length of the data read, write sn_RX_BASE, and finally write the RECV command to the instruction register on port n.

“Send data?”/”send process” is implemented by first reading the value of the S_TX_FSR register so that the size of the send data space can be used to calculate the offset and the actual physical address, and then writing the data to be sent from the physical address. When sending data, if the physical address has reached the high limit address set for the port, the data is written to the high limit address first, then the physical address is changed to the base address, and then the data is written from the base address. After writing all the data, add the value of Sn_TX_WR and the length of the data sent, then write Sn_TX_BASE, and finally write SEND command to the instruction register of port n. After sending the command, the value of Sn_CR can be detected to determine whether all the data has been sent.

A timeout error occurs when the remote counterpart does not exist or when the data transfer is abnormal. This TIMEOUT can be determined by detecting Sn_IR (TIMEOUT bit). When the operation is complete, the window should be closed, setting the Sn_CR register to CLOSE.


This paper introduces the design of Ethernet interface and the realization process of data transmission. The method in this paper can make Ethernet interface run normally, so it can lay a foundation for the development of virtual instrument.

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