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Sep 30 2019

EPF8636ALC84-3 Datasheet PDF – IC FPGA 68 I/O 84PLCC Altera

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-EPF8636ALC84-3

Manufacturer Part#:

EPF8636ALC84-3

Manufacturer

Altera

Description:

IC FPGA 68 I/O 84PLCC

Package:

84-LCC (J-Lead)

Datasheet:

EPF8636ALC84-3 Datasheet

Stock:

Yes

Quantity:

2308 PCS

EPF8636ALC84-3 Images are for reference only:

EPF8636ALC84-3


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Altera

Series

FLEX 8000

Product

FLEX 8000

Packaging

Tube

Package/Case

84-LCC (J-Lead)

Copy Protection

No

Clock Frequency-Max

385.0 MHz

Device System Gates

6000

Device Logic Units

504

Device Logic Gates

6000

Frequency

125 MHz

Family Name

FLEX 8000

In-System Programmability

No

JESD-30 Code

S-PQCC-J84

JESD-609 Code

e0

Lead Shape

J-Lead

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

3

Number of I/O Lines

68.0

Number of Pins

84

Number of Inputs

68.0

Number of Logic Cells

504.0

Number of Outputs

64.0

Number of Terminals

84

Number of Registers

636

Number of LABs/CLBs

63

Number of Dedicated Inputs

4.0

Organization

4 DEDICATED INPUTS, 68 I/O

Output Function

REGISTERED

Operating Temperature-Min

0°C

Operating Temperature-Max

70.0°C

Operating Supply Current

10 mA

Pin Count

84

PCB changed

84

Package Body Material

PLASTIC/EPOXY

Package Code

QCCJ

Package Equivalence Code

LDCC84,1.2SQ

Package Shape

SQUARE

Package Style

CHIP CARRIER

Process Technology

0.42 um

Peak Reflow Temperature

220°C

Power Supplies

5

Programmability

No

Program Memory Type

SRAM

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Product Type

FPGA - Field Programmable Gate Array

RAM Size

1 B

Reprogrammability Support

Yes

Speed Grade

3

Seated Height-Max

5.08 mm

Sub Category

Field Programmable Gate Arrays

Supply Voltage-Nom

5.0 V

Supply Voltage-Min

4.75 V

Supply Voltage-Max

5.25 V

Surface Mount

Yes

Supplier Device Package

84-PLCC (29.21x29.21)

Tradename

FLEX 8000

Technology

CMOS

Terminal Finish

Tin/Lead (Sn/Pb)

Terminal Form

J BEND

Terminal Pitch

1.27 mm

Terminal Position

QUAD

Temperature Grade

COMMERCIAL

Time@Peak Reflow Temperature-Max

30 s

Length

29.3116 mm

Width

29.3116 mm

Voltage-Supply

4.75 V ~ 5.25 V

RoHS Compliant

Yes

Lead Free Status

Lead Free


EPF8636ALC84-3 Datasheet PDF Download:

EPF8636ALC84-3 Datasheet PDF

Block Diagram

FLEX 8000 Device Block Diagram

FLEX 8000 Device Block Diagram


Description

Altera’s Flexible Logic Element MatriX (FLEX®) family combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained

architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources.

FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device.

Features

Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family

    2,500 to 16,000 usable gates

    282 to 1,500 registers

■ System-level features

    In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller

   Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation

   Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices

    MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels

    Low power consumption (typical specification is 0.5 mA or less in standby mode)

■ Flexible interconnect

   FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays

    Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)

    – Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)

   Tri-state emulation that implements internal tri-state nets

■ Powerful I/O pins

■ Programmable output slew-rate control reduces switching noise

■ Peripheral register for fast setup and clock-to-output delay

■ Fabricated on an advanced SRAM process

■ Available in a variety of packages with 84 to 304 pins

■ Software design support and automatic place-and-route provided by the Altera® MAX+PLUS® II development system for Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations

Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest


Other data sheets within the file:

Datasheet

EPF8636ALC84-3 Datasheet

EPF8636ALC84-3 Datasheet

84PLCC Pkg Info

84PLCC Pkg Info


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