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Apr 25 2019

EP4SGX360KF43C2N Datasheet PDF - IC Stratix IV GX FPGA 880 I/O 1760FBGA INTEL

Product Overview

Product Category:

IC Chips

Kynix Part #:

KY32-EP4SGX360KF43C2N

Manufacturer Part#:

EP4SGX360KF43C2N

Manufacturer

Intel / Altera

Description:

IC FPGA 880 I/O 1760FBGA

Package:

FPGA - Field Programmable Gate Array

Datasheet:

EP4SGX360KF43C2N Datasheet

Stock:

Yes

Quantity:

99 PCS


EP4SGX360KF43C2N Images are for reference only:

EP4SGX360KF43C2N Image

Product Specifications

Categories

Integrated Circuits (ICs)

Embedded - FPGAs (Field Programmable Gate Array)

Subcategory

Programmable Logic ICs

Series

Stratix® IV GX

State

Active

Data Rate

600 Mb/s to 8.5 Gb/s

Ethernet MACs

1

Part Status

Active

Number of LABs/CLBs

14144

Number of Logic Elements/Cells

353600

Number of DLLs/PLLs

12

Total RAM Bits

23105536

Number of I/O 

880

Differential I/O Standards Supported

LVPECL|LVDS

Single-Ended I/O Standards Supported

LVTTL|CMOS|PCI|PCI-X

Voltage - Supply

0.87V ~ 0.93V

Lead Shape

Ball

Mounting Type

Surface Mount

Maximum Operating Frequency

600 MHz

Number of Logic Elements

353600

Number of Logic Array Blocks - LABs

14144

Number of Transceivers

36 Transceiver

Number of SERDES Channels (MAX)

88

Operating Supply Voltage

900 mV

Operating Temperature

0°C ~ 85°C (TJ)

Maximum Reflow Temperature

245 °C

Programmability

Yes

Packaging

Tray

Pin Count

1760

PCB

1760

Package / Case

1760-BBGA, FCBGA

Product

Stratix IV GX

Package Length

42.5 mm

Package Width

42.5 mm

Package Height

2.8 mm

Pin Pitch

1 mm

Program Memory Type

SRAMs

Package Material

Plastic

Process Technology

40nm

Supplier Device Package

1760-FBGA, FC (42.5x42.5)

Speed Grade

2

Total Memory

22564 kbit

Transceiver Blocks

24

Transceiver Speed

8.5Gbpss

Base Part Number

EP4SGX360

ECCN

3A001.a.7.a

HTSUSA

8542390001

Product Type

FPGA - Field Programmable Gate Array

Brand

Intel / Altera

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Moisture Sensitivity Level (MSL)

3 (168 Hours)


EP4SGX360KF43C2N Datasheet PDF Download:

EP4SGX360KF43C2N Datasheet PDF 

Pinouts

There is no relevant information available for this part yet.

Description

The Stratix IV device family contains three optimized variants to meet different application requirements:

■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits (Kb) RAM, and 1,288 18 x 18 bit multipliers

■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps

■ Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps

The complete Altera high-end solution includes the lowest risk, lowest total cost path to volume using HardCopy® IV ASICs for all the family variants, a comprehensive portfolio of application solutions customized for end-markets, and the industry leading Quartus® II software to increase productivity and performance.

Features

The following list summarizes the Stratix IV device family features:

■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken

■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality 

■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium

■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel

■ 72,600 to 813,050 equivalent LEs per device

■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers

■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device

■ Programmable power technology that minimizes power while maximizing device performance

■ Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards

■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

■ High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps

■ Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■ Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact

Other data sheets within the file:

Part Number

EP4SGX360KF43C2N Datasheet

Description

FPGA Stratix® IV GX Family 353600 Cells 40nm Technology 0.9V 1760-Pin FC-FBGA

EP4SGX360KF43C2N Datasheet


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