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Dec 6 2019

EP4SGX230KF40I3N Datasheet PDF - IC FPGA 744 I/O 1517FBGA Altera

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-EP4SGX230KF40I3N

Manufacturer Part#:

EP4SGX230KF40I3N

Manufacturer

Freescale Semiconductor - NXP

Description:

IC FPGA 744 I/O 1517FBGA

Package:

1517-BBGA, FCBGA

Datasheet:

EP4SGX230KF40I3N Datasheet

Stock:

Yes

Quantity:

319 PCS


EP4SGX230KF40I3N Images are for reference only:

EP4SGX230KF40I3N Image 

Product Specifications 

Categories

Integrated Circuits (ICs) Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Intel

Series

Stratix® IV GX

Packaging

Tray

Part Status

Active

Number of LABs/CLBs

9120

Number of Logic Elements/Cells

228000

Total RAM Bits

17544192

Number of I/O

744

Voltage - Supply

0.87V ~ 0.93V

Mounting Type

Surface Mount

Operating Temperature

-40°C ~ 100°C (TJ)

Package / Case

1517-BBGA, FCBGA

Supplier Device Package

1517-FBGA (40x40)

Base Part Number

EP4SGX230

Mfr Package Description

LEAD FREE, FBGA-1517

EU RoHS Compliant

Yes

Status

Transferred

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Clock Frequency-Max

717.0  MHz

JESD-30 Code

S-PBGA-B1517

JESD-609 Code

e1

Moisture Sensitivity Level

3

Number of CLBs

91200.0

Number of Inputs

744.0

Number of Logic Cells

228000.0

Number of Outputs

744.0

Number of Terminals

1517

Organization

91200 CLBS

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Equivalence Code

BGA1517,39X39,40

Package Shape

SQUARE

Package Style

GRID ARRAY

Peak Reflow Temperature (Cel)

245

Power Supplies

0.9,1.2/3,1.5,2.5

Qualification Status

Not Qualified

Seated Height-Max

3.6  mm

Sub Category

Field Programmable Gate Arrays

Supply Voltage-Nom

0.9  V

Supply Voltage-Min

0.87  V

Supply Voltage-Max

0.93  V

Surface Mount

YES

Technology

CMOS

Terminal Finish

Tin/Silver/Copper (Sn/Ag/Cu)

Terminal Form

BALL

Terminal Pitch

1.0  mm

Terminal Position

BOTTOM

Time@Peak Reflow Temperature-Max (s)

40

Length

40.0  mm

Width

40.0  mm


EP4SGX230KF40I3N Datasheet PDF Download:

EP4SGX230KF40I3N Datasheet PDF

Block Diagram

There is no relevant information available for this part yet.

Pin Assignments

There is no relevant information available for this part yet.

Description

Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.

Features

■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken

■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality. For more information, refer to the IP Compiler for PCI Express User Guide

■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium

■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel

■ 72,600 to 813,050 equivalent LEs per device

■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers

■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device

■ Programmable power technology that minimizes power while maximizing device performance

 Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards

■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

■ High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps

■ Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■ Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact

Other data sheets within the file:

Datasheets

Stratix IV Device Handbook Vol1

Stratix IV Device Handbook Vol1

Stratix IV Device Handbook Vol.1

Stratix IV Device Handbook Vol.1

Stratix IV GX Errata

Stratix IV GX Errata

Virtual JTAG Megafuntion User Guide

Virtual JTAG Megafuntion User Guide

Stratix IV Device Handbook Vol1

Stratix IV Device Handbook Vol1

PCN Design/Specification

Mult Dev Add Subs 6/Sep/2019

Mult Dev Add Subs 6/Sep/2019

All Dev Pkg Chg 1/Aug/2018

All Dev Pkg Chg 1/Aug/2018

Mult Dev Dessicant Chg 19/Jul/2019

Mult Dev Dessicant Chg 19/Jul/2019

Readiness Plan 18/Jan/2019

Readiness Plan 18/Jan/2019

 


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