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Jan 9 2020

EP4SE230F29C3N Datasheet PDF – IC FPGA 488 I/O 780FBGA Altera

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-EP4SE230F29C3N

Manufacturer Part#:

EP4SE230F29C3N

Manufacturer

Altera

Description:

IC FPGA 488 I/O 780FBGA

Package:

780-BBGA, FCBGA

Datasheet:

EP4SE230F29C3N Datasheet

Stock:

Yes

Quantity:

69 PCS


EP4SE230F29C3N Images are for reference only:

EP4SE230F29C3N


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Altera

Status

Active

Series

STRATIX® IV E

Copy Protection

Yes

Clock Frequency-Max

717.0 MHz

Dedicated DSP

161

Device Logic Units

228000

Device Number of DLLs/PLLs

4

EMACs

1

Embedded Memory

17133 Kbit

EU RoHS Compliant

Yes

Family Name

Stratix® IV E

In-System Programmability

No

JESD-30 Code

S-PBGA-B780

JESD-609 Code

e1

Lead Shape

Ball

Memory Size

2.1 MB

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

4

Maximum Operating Frequency

600 MHz

Number of I/Os

488

Number of Pins

780

Number of Inputs

488.0

Number of Logic Cells

228000.0

Number of Outputs

488.0

Number of Registers

182400

Number of I/O Banks

24

Number of Terminals

780

Number of Multipliers

1288 (18x18)

Number of LABs/CLBs

9120

Number of Global Clocks

16

Organization

9120 CLBS

Operating Temperature-Min

0.0°C

Operating Temperature-Max

85.0°C

Pin Count

780

PCB changed

780

Package / Case

780-BBGA, FCBGA

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Equivalence Code

BGA780,28X28,40

Package Shape

SQUARE

Package Style

GRID ARRAY

Peak Reflow Temperature

245°C

Power Supplies

0.9,1.2/3,1.5,2.5

Process Technology

40 nm

Programmability

Yes

Program Memory Type

SRAM

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Product Type

FPGA - Field Programmable Gate Array

RAM Size

2.1 MB

Reprogrammability Support

No

Speed Grade

3

Shift Registers

Utilize Memory

Seated Height-Max

3.4 mm

Sub Category

Field Programmable Gate Arrays

SERDES Channels

56

Supply Voltage-Nom

0.9 V

Supply Voltage-Min

0.87 V

Supply Voltage-Max

0.93 V

Surface Mount

Yes

Supplier Device Package

780-FBGA (29x29)

Tradename

Stratix

Technology

CMOS

Total Memory

17133 kbit

Total RAM Bits

17544192

Terminal Finish

Tin/Silver/Copper (Sn/Ag/Cu)

Terminal Form

BALL

Terminal Pitch

1.0 mm

Terminal Position

BOTTOM

Transceiver Speed

11.3 Gbps

Transceiver Channels

16

Temperature Grade

OTHER

Time@Peak Reflow Temperature-Max

40 s

Length

29.0 mm

Width

29.0 mm

Voltage-Supply

0.87 V ~ 0.93 V

RoHS Compliant

Yes

Lead Free Status

Lead Free


EP4SE230F29C3N Datasheet PDF Download:

EP4SE230F29C3N Datasheet PDF

Ordering Information

Figure 1. Stratix IV GX and E Device Packaging Ordering Information 

Figure 1. Stratix IV GX and E Device Packaging Ordering Information

Figure 2. Stratix IV GT Device Packaging Ordering Information

Figure 2. Stratix IV GT Device Packaging Ordering Information

Description

Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.

The Stratix IV device family contains three optimized variants to meet different application requirements:

■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits (Kb) RAM, and 1,288 18 x 18 bit multipliers

■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps

■ Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps

The complete Altera high-end solution includes the lowest risk, lowest total cost path to volume using HardCopy® IV ASICs for all the family variants, a comprehensive portfolio of application solutions customized for end-markets, and the industry leading Quartus® II software to increase productivity and performance.

Features

■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken

■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality

■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium

Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel

72,600 to 813,050 equivalent LEs per device

7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers

High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device

Programmable power technology that minimizes power while maximizing device performance

Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards

Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps

Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact


Other data sheets within the file:

Datasheet

EP4SE230F29C3N Datasheet

EP4SE230F29C3N Datasheet

Stratix IV Device Family Overview

Stratix IV Device Family Overview

Stratix IV Device Handbook Vol.1

Stratix IV Device Handbook Vol.1

Stratix IV E Errata

Stratix IV E Errata

Stratix IV Devices

Stratix IV Devices

Virtual JTAG Megafuntion User Guide

Virtual JTAG Megafuntion User Guide


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