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Sep 30 2019

EP3SL110F780I4N Datasheet PDF – IC FPGA 488 I/O 780FBGA Altera

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32- EP3SL110F780I4N

Manufacturer Part#:

EP3SL110F780I4N

Manufacturer

Altera

Description:

IC FPGA 488 I/O 780FBGA

Package:

780-BBGA, FCBGA

Datasheet:

EP3SL110F780I4N Datasheet

Stock:

Yes

Quantity:

92 PCS


EP3SL110F780I4N Images are for reference only:

EP3SL110F780I4N


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Altera

Series

Stratix® III L

Packaging

Tray

Package/Case

780-BBGA, FCBGA

Clock Frequency-Max

717.0 MHz

EU RoHS Compliant

Yes

Embedded Block RAM - EBR

672 kbit

Frequency

450 MHz

JESD-30 Code

S-PBGA-B780

JESD-609 Code

e1

Memory Size

1.1 MB

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

3

Number of I/O

488

Number of Pins

780

Number of Inputs

488.0

Number of Logic Cells

107500.0

Number of Outputs

488.0

Number of Terminals

780

Number of LABs/CLBs

4300

Operating Temperature-Min

-40.0 °C

Operating Temperature-Max

100.0 °C

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Equivalence Code

BGA780,28X28,40

Package Shape

SQUARE

Package Style

GRID ARRAY

Power Supplies

1.2/3.3

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Product Type

FPGA - Field Programmable Gate Array

RAM Size

609.4 kB

Seated Height-Max

3.5 mm

Sub Category

Field Programmable Gate Arrays

Voltage-Supply

0.86 V ~ 0.94 V

Supply Voltage-Nom

0.9 V

Supply Voltage-Min

0.86 V

Supply Voltage-Max

0.94 V

Supplier Device Package

780-FBGA (29x29)

Surface Mount

Yes

Tradename

Stratix

Technology

CMOS

Terminal Finish

Tin/Silver/Copper (Sn/Ag/Cu)

Terminal Form

BALL

Terminal Pitch

1.0 mm

Terminal Position

BOTTOM

Total Memory

8727 kbit

Total RAM Bits

4992000

Length

29.0 mm

Width

29.0 mm

RoHS Compliant

Yes

Lead Free Status

Lead Free


EP3SL110F780I4N Datasheet PDF Download:

EP3SL110F780I4N Datasheet PDF


Description

The Stratix® III family provides one of the most architecturally advanced, high-performance, low-power FPGAs in the marketplace. 

Stratix III FPGAs lower power consumption through Alteras innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industrys lowest power, high-performance FPGAs.  

Specifically designed for ease of use and rapid system integration, the Stratix III FPGA family offers two variants optimized to meet different application needs:

The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications.

The Stratix III E family is memory- and multiplier-rich for data-centric applications. Modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high-speed I/O. Package and die enhancements with dynamic on-chip termination, output delay, and current strength control provide best-in-class signal integrity.

Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a programmable alternative to custom ASICs and programmable processors for high-performance logic, digital signal processing (DSP), and embedded designs.

Stratix III devices include optional configuration bit stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, Stratix III devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells.

Features

48,000 to 338,000 equivalent logic elements (LEs)

2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers

High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters

■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity

■ Programmable Power Technology, which minimizes power while maximizing device performance

Selectable Core Voltage, available in low-voltage devices (L ordering code suffix), enables selection of lowest power or highest performance operation

■ Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device

Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis, and dynamic phase shifting

■ Memory interface support with dedicated DQS logic on all I/O banks

Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards

Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O banks

High-speed differential I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance

Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI

The only high-density, high-performance FPGA with support for 256-bit AES volatile and non-volatile security key to protect designs

■ Robust on-chip hot socketing and power sequencing support

Integrated cyclical redundancy check (CRC) for configuration memory error detection with critical error determination for high availability systems support

■ Built-in error correction coding (ECC) circuitry to detect and correct data errors in M144K TriMatrix memory blocks

■ Nios® II embedded processor support

■ Support for multiple intellectual property megafunctions fromAltera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)


Other data sheets within the file:

Datasheet

EP3SL110F780I4N Datasheet

EP3SL110F780I4N Datasheet

Stratix III Device Handbook

Stratix III Device Handbook

Virtual JTAG Megafuntion User Guide

Virtual JTAG Megafuntion User Guide


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