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Oct 19 2019

EP3C55F780C7N Datasheet PDF – IC FPGA 377 I/O 780FBGA Altera

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-EP3C55F780C7N

Manufacturer Part#:

EP3C55F780C7N

Manufacturer

Altera

Description:

IC FPGA 377 I/O 780FBGA

Package:

780-BGA

Datasheet:

EP3C55F780C7N Datasheet

Stock:

Yes

Quantity:

2356 PCS


EP3C55F780C7N Images are for reference only:

EP3C55F780C7N

 


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Altera

Status

Active

Series

Cyclone® III

Packaging

Tray

Package-Case

780-BGA

Clock Frequency-Max

472.5 MHz

Copy Protection

Yes

China RoHS Compliant

Yes

EU RoHS Compliant

Yes

External Memory Interface

DDR2 SDRAM|QDRII+SRAM

In-System Programmability

No

JESD-30 Code

R-PBGA-B780

JESD-609 Code

e1

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

3

Maximum-Operating-Frequency

315 MHz

Number of I/O

377

Number of I/O Banks

8

Number of Inputs

377.0

Number of Logic Cells

55856.0

Number of Outputs

377.0

Number of Pins

780

Number of Terminals

780

Number of Multipliers

156 (18x18)

Number of LABs/CLBs

3491

Number of Global Clocks

20

Device Number of DLLs/PLLs

4

Number of Logic Elements/Cells

55856

Organization

55856 CLBS

Operating Temperature-Min

0.0°C

Operating Temperature-Max

85.0°C

Pin Count

780

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Equivalence Code

BGA780,28X28,40

Package Shape

RECTANGULAR

Package Style

GRID ARRAY

Peak Reflow Temperature

245°C

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Program Memory Type

SRAM

Programmability

No

Process Technology

65 nm

RAM Size

292.5 kB

Reprogrammability Support

No

Supplier Temperature Grade

Commercial

Seated Height-Max

3.5 mm

Sub Category

Field Programmable Gate Arrays

Voltage-Supply

1.15 V ~ 1.25 V

Supply Voltage-Nom

1.2 V

Supply Voltage-Min

1.15 V

Supply Voltage-Max

1.25 V

Surface Mount

Yes

Technology

CMOS

Terminal Finish

Tin/Silver/Copper (Sn/Ag/Cu)

Terminal Form

BALL

Terminal Pitch

1.0 mm

Terminal Position

BOTTOM

Total-Memory

2396160 bit

Total RAM Bits

2396160

Temperature Grade

OTHER

Total Number of Block RAM

260

Tradename

Cyclone III

Time@Peak Reflow Temperature-Max

40 s

Length

29.0 mm

Width

29.0 mm


EP3C55F780C7N Datasheet PDF Download: 

EP3C55F780C7N Datasheet PDF


Description

Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost

■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.

Features

Cyclone III device family offers the following features:

• Lowest Power FPGAs

■ Lowest power consumption with TSMC low-power process technology and Altera® power-aware design flow

■ Low-power operation offers the following benefits:

■ Extended battery life for portable and handheld applications

■ Reduced or eliminated cooling system costs

■ Operation in thermally-challenged environments

■ Hot-socketing operation support

• Design Security Feature

■ Configuration security using advanced encryption standard (AES) with 256-bit volatile key

■ Routing architecture optimized for design separation flow with the Quartus® II software

■ Design separation flow achieves both physical and functional isolation between design partitions

■ Ability to disable external JTAG port

■ Error Detection (ED) Cycle Indicator to core

■ Provides a pass or fail indicator at every ED cycle

■ Provides visibility over intentional or unintentional change of configuration random access memory (CRAM) bits

■ Ability to perform zeroization to clear contents of the FPGA logic, CRAM, embedded memory, and AES key

■ Internal oscillator enables system monitor and health check capabilities

• Increased System Integration

■ High memory-to-logic and multiplier-to-logic ratio

■ High I/O count, low-and mid-range density devices for user I/O constrained applications

■ Adjustable I/O slew rates to improve signal integrity

■ Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS

■ Supports the multi-value on-chip termination (OCT) calibration feature to eliminate variations over process, voltage, and temperature (PVT)

■ Four phase-locked loops (PLLs) per device provide robust clock management and synthesis for device clock management, external system clock management, and I/O interfaces

■ Five outputs per PLL

■ Cascadable to save I/Os, ease PCB routing, and reduce jitter

■ Dynamically reconfigurable to change phase shift, frequency multiplication or division, or both, and input frequency in the system without reconfiguring the device

■ Remote system upgrade without the aid of an external controller

■ Dedicated cyclical redundancy code checker circuitry to detect single-event upset (SEU) issues

■ Nios® II embedded processor for Cyclone III device family, offering low cost and custom-fit embedded processing solutions

■ Wide collection of pre-built and verified IP cores from Altera and Altera Megafunction Partners Program (AMPP) partners

■ Supports high-speed external memory interfaces such as DDR, DDR2, SDR SDRAM, and QDRII SRAM

■ Auto-calibrating PHY feature eases the timing closure process and eliminates variations with PVT for DDR, DDR2, and QDRII SRAM interfaces 

Cyclone III device family supports vertical migration that allows you to migrate your device to other devices with the same dedicated pins, configuration pins, and power pins for a given package-across device densities. This allows you to optimize device density and cost as your design evolves.


Other data sheets within the file:

Datasheet

EP3C55F780C7N Datasheet

EP3C55F780C7N Datasheet

Cyclone III Family Overview

Cyclone III Family Overview

Cyclone III FPGA Family Errata

Cyclone III FPGA Family Errata

Cyclone III Device Handbook Vol1

Cyclone III Device Handbook Vol1

Virtual JTAG Megafuntion User Guide

Virtual JTAG Megafuntion User Guide


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