Home  FPGAs

Jan 9 2020

EP2AGX65DF29I3N Datasheet PDF – IC FPGA 364 I/O 780FBGA Altera

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-EP2AGX65DF29I3N

Manufacturer Part#:

EP2AGX65DF29I3N

Manufacturer

Altera

Description:

IC FPGA 364 I/O 780FBGA

Package:

780-BBGA, FCBGA

Datasheet:

EP2AGX65DF29I3N Datasheet

Stock:

Yes

Quantity:

474 PCS


EP2AGX65DF29I3N Images are for reference only:

EP2AGX65DF29I3N 


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Altera

Series

Arria II GX

Clock Frequency-Max

500.0 MHz

Data Rate

600 Mb/s to 6.375 Gb/s

EU RoHS Compliant

Yes

Embedded Block RAM - EBR

791 kbit

Frequency

500 MHz

JESD-30 Code

S-PBGA-B780

JESD-609 Code

e1

Memory Size

655.8 kB

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

3

Maximum Operating Frequency

390 MHz

Number of I/Os

364

Number of Pins

780

Number of Inputs

364.0

Number of Logic Cells

60214.0

Number of Outputs

364.0

Number of Terminals

780

Number of LABs/CLBs

2530

Number of Transceivers

8

Operating Temperature-Min

-40.0°C

Operating Temperature-Max

100.0°C

Package / Case

780-BBGA, FCBGA

Package Body Material

PLASTIC/EPOXY

Package Code

HBGA

Package Equivalence Code

BGA780,28X28,40

Package Shape

SQUARE

Package Style

GRID ARRAY, HEAT SINK/SLUG

Peak Reflow Temperature

NOT SPECIFIED

Power Supplies

0.9,1.2/3,1.5,2.5

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Product Type

FPGA - Field Programmable Gate Array

RAM Size

655.8 kB

REACH Compliant

Yes

Seated Height-Max

2.7 mm

Sub Category

Field Programmable Gate Arrays

Supply Voltage-Nom

0.9 V

Supply Voltage-Min

0.87 V

Supply Voltage-Max

0.93 V

Surface Mount

Yes

Supplier Device Package

780-FBGA (29x29)

Tradename

Arria

Technology

CMOS

Total Memory

5246 kbit

Total RAM Bits

5371904

Terminal Finish

TIN SILVER COPPER

Terminal Form

BALL

Terminal Pitch

1.0 mm

Terminal Position

BOTTOM

Temperature Grade

INDUSTRIAL

Time@Peak Reflow Temperature-Max

NOT SPECIFIED

Length

29.0 mm

Width

29.0 mm

Voltage-Supply

0.87 V ~ 0.93 V


EP2AGX65DF29I3N Datasheet PDF Download:

EP2AGX65DF29I3N Datasheet PDF

Ordering Information

Figure 1. Packaging Ordering Information for Arria II Devices

Figure 1. Packaging Ordering Information for Arria II Devices

Structure

Figure 2. LAB Structure in Arria II Devices

Figure 2. LAB Structure in Arria II Devices

Block Diagram

Figure 3. High-Level Block Diagram of the Arria II ALM 

Figure 3. High-Level Block Diagram of the Arria II ALM

Description

The Arria® II device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine and streamlined transceivers and I/Os. Common interfaces, such as the Physical Interface for PCI Express® (PCIe®), Ethernet, and DDR3 memory are easily implemented in your design with the Quartus® II software, the SOPC Builder design software, and a broad library of hard and soft intellectual property (IP) solutions from Altera. The Arria II device family makes designing for applications requiring transceivers operating at up to 6.375 Gbps fast and easy

■ 40-nm, low-power FPGA engine

■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry

■ Eight-input fracturable look-up table (LUT)

■ Memory logic array blocks (MLABs) for efficient implementation of small FIFOs

■ High-performance digital signal processing (DSP) blocks up to 550 MHz

■ Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers as well as 18 x 36-bit high-precision multiplier

■ Hardcoded adders, subtractors, accumulators, and summation functions

■ Fully-integrated design flow with the MATLAB and DSP Builder software from Altera

■ Maximum system bandwidth

■ Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting rates between 600 Mbps and 6.375 Gbps

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, including PCIe Gen1 and PCIe Gen2, Gbps Ethernet, Serial RapidIO® (SRIO), Common Public Radio Interface (CPRI), OBSAI, SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI (RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON, SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter (JESD204), and SFI-5.

Complete PIPE protocol solution with an embedded hard IP block that provides physical interface and media access control (PHY/MAC) layer, Data Link layer, and Transaction layer functionality

Optimized for high-bandwidth system interfaces

Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a wide range of single-ended and differential I/O standards

High-speed LVDS I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to 1.25 Gbps

Low power

Architectural power reduction techniques

Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps.

Power optimizations integrated into the Quartus II development software

Advanced usability and security features

Parallel and serial configuration options

On-chip series (RS) and on-chip parallel (RT) termination with auto-calibration for single-ended I/Os and on-chip differential (RD) termination for differential I/O

256-bit advanced encryption standard (AES) programming file encryption for design security with volatile and non-volatile key storage options

Robust portfolio of IP for processing, serial protocols, and memory interfaces

Low cost, easy-to-use development kits featuring high-speed mezzanine connectors (HSMC)

Emulated LVDS output support with a data rate of up to 1152 Mbps


Other data sheets within the file:

Datasheet

EP2AGX65DF29I3N Datasheet

EP2AGX65DF29I3N Datasheet

Arria II Device Handbook

Arria II Device Handbook

Arria II Device Handbook Vol 3

Arria II Device Handbook Vol 3

Arria II GX Errata

Arria II GX Errata

Virtual JTAG Megafuntion User Guide

Virtual JTAG Megafuntion User Guide


0 comment

Leave a Reply

Your email address will not be published.

 
 
   
Rating: