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Sep 30 2019

EP1S60B956C6 Datasheet PDF – IC FPGA 683 I/O 956BGA Altera

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32- EP1S60B956C6

Manufacturer Part#:

EP1S60B956C6

Manufacturer

Altera

Description:

IC FPGA 683 I/O 956BGA

Package:

956-BBGA, FCBGA

Datasheet:

EP1S60B956C6 Datasheet

Stock:

Yes

Quantity:

575 PCS

EP1S60B956C6 Images are for reference only:

EP1S60B956C6


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Altera

Series

Stratix®

Product

Stratix

Packaging

Tray

Package/Case

956-BBGA

Frequency

450.05 MHz

JESD-30 Code

S-PBGA-B956

JESD-609 Code

e0

Memory Size

636.6 kB

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

3

Maximum-Operating-Frequency

100 MHz

Number of I/O

683

Number of Pins

956

Number of Inputs

1022.0

Number of Logic Cells

57120.0

Number of Outputs

1022.0

Number of Terminals

956

Number of LABs/CLBs

5712

Organization

6570 CLBS

Operating Temperature-Min

0°C

Operating Temperature-Max

85.0°C

Operating Supply Current

200 mA

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Equivalence Code

BGA956,31X31,50

Package Shape

SQUARE

Package Style

GRID ARRAY

Peak Reflow Temperature

220°C

Power Supplies

1.5,1.5/3.3

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Product Type

FPGA - Field Programmable Gate Array

RAM Size

636.6 kB

Seated Height-Max

3.5 mm

Sub Category

Field Programmable Gate Arrays

Voltage-Supply

1.425 V ~ 1.575 V

Supply Voltage-Nom

1.5 V

Supply Voltage-Min

1.425 V

Supply Voltage-Max

1.575 V

Surface Mount

Yes

Tradename

Stratix

Technology

CMOS

Terminal Finish

Tin/Lead (Sn63Pb37)

Terminal Form

BALL

Terminal Pitch

1.27 mm

Terminal Position

BOTTOM

Total Memory

5215104 bit

Total RAM Bits

5215104

Temperature Grade

COMMERCIAL EXTENDED

Time@Peak Reflow Temperature-Max

30 s

Length

40.0 mm

Width

40.0 mm

RoHS Compliant

Yes

Lead Free Status

Lead Free


EP1S60B956C6 Datasheet PDF Download:

EP1S60B956C6 Datasheet PDF

Block Diagram

EP1S60B956C6 Block Diagram

EP1S60B956C6 Block Diagram

LAB Structure

LAB Structure

LAB Structure

Package Outline

956-Pin BGA Package Outline

956-Pin BGA Package Outline


Description

The Stratix® family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).

Features

10,570 to 79,040 LEs;

Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources

TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers

High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters

■ Up to 16 global clocks with 22 clocking resources per device region

Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting

■ Support for numerous single-ended and differential I/O standards

High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps)

Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4

■ Differential on-chip termination support for LVDS

Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM

Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices

■ Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices

■ Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices

■ Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices

Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions

■ Support for remote configuration updates


Other data sheets within the file:

Datasheet

EP1S60B956C6 Datasheet

EP1S60B956C6 Datasheet

Stratix Device Handbook

Stratix Device Handbook

956-BGA Pkg Info

956-BGA Pkg Info

Virtual JTAG Megafuntion User Guide

Virtual JTAG Megafuntion User Guide


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