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Oct 8 2019

DSPD56371AF180 Datasheet PDF - IC 24-Bit Size CMOS PQFP80 NXP

Product Overview

Product Category:

IC Chips

Kynix Part #:

KY32-DSPD56371AF180

Manufacturer Part#:

DSPD56371AF180

Manufacturer

NXP USA Inc.

Description:

-

Package:

QFP

Datasheet:

DSPD56371AF180 Datasheet

Stock:

Yes

Quantity:

2467 PCS


DSPD56371AF180 Images are for reference only:

DSPD56371AF180 Image 

Product Specifications 

Categories

Integrated Circuits (ICs)

Embedded - Microcontrollers

Series

-

Status

Custom

EU RoHS Compliant

Yes

Brand

NXP / Freescale

Bit Size

24

Connectivity

I2C/SPI

Data Bus Width

24 Bit

Device Input Clock Speed

181 MHz

Device Million Instructions per Second

181 MIPS

Device Core

DSP56300

Device Input Clock Speed

181 MHz

ECCN (US)

3A991.a.2

Format

FIXED-POINT

Halogen Free

Halogen Free

HTS

8542.31.00.01

JESD-30 Code

S-PQFP-G80

JESD-609 Code

e3

Lead Free

Lead Free

Max Processing Temp

260

Moisture Sensitive

Yes

Mounting Style

SMD/SMT

Number of I/Os

39

Number of Programmable I/O

39

Number of Pins

80

Number of USART Channels

0

Number of UART Channels

0

Numeric and Arithmetic Format

Fixed-Point

Number of CAN Channels

0

Number of I2C Channels

1

Number of I2S Channels

0

Number of SPI Channels

1

Ethernet

0

Height

1.5 mm

Length

14 mm

Width

14 mm

Oscillator Type

Internal

Operating Temperature

-40°C ~ 115°C (TA)

Packaging

Tray

Programmability

Yes

Product Category

Digital Signal Processors & Controllers - DSP, DSC

Product Type

DSP - Digital Signal Processors & Controllers

Program Memory Type

ROM

Program Memory Size

192 Kb

Product Dimensions

14 x 14 x 1.5 mm

PCB changed

80

Package Body Material

PLASTIC/EPOXY

Package Code

QFP

Package Equivalence Code

QFP80,.64SQ

Package Shape

SQUARE

Package Style

FLATPACK

Power Supplies

1.25,3.3 V

Qualification Status

Not Qualified

RAM Size

264 KB

Radiation Hardening

No

RoHS

Compliant

Rohs Code

Yes

RAM (words)

86016

ROM Programmability

FLASH

Risk Rank

5.47

Speed

181 MHz

Supply Voltage-Max

1.3|3.46 V

Supply Voltage-Min

1.2|3.14 V

Supply Voltage-Nom

1.25|3.3 V

Subcategory

Digital Signal Processors

Technology

CMOS

Temperature Grade

INDUSTRIAL

Terminal Finish

Matte Tin (Sn)

Terminal Form

GULL WING

Terminal Pitch

0.635 mm

Terminal Position

QUAD

Moisture Sensitivity Level (MSL)

3 (168 Hours)


DSPD56371AF180 Datasheet PDF Download:

DSPD56371AF180 Datasheet PDF

Block Diagram

DSP56371 Block Diagram 

Fig. 1 DSP56371 Block Diagram

Signals Identified by Functional Group 

Fig. 2 Signals Identified by Functional Group

Description

The DSP56371 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. 

The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code compatibility with it.

Features

• DSP56300 modular chassis

— 181 Million Instructions Per Second (MIPS) with a 181 MHz clock at an internal logic supply

(QVDDL) of 1.25 V

— Object Code Compatible with the 56K core

— Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit

arithmetic support

— Program Control with position independent code support and instruction patch support

— EFCOP running concurrently with the core, capable of executing 181 million filter taps per

second at peak performance

— Six-channel DMA controller

— Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 255),

predivider factors (1 to 31) and power saving clock divider (2i : i=0 to 7). Reduces clock noise.

— Internal address tracing support and OnCE for Hardware/Software debugging

— JTAG port

— Very low-power CMOS design, fully static design with operating frequencies down to DC

— STOP and WAIT low-power standby modes

• On-chip Memory Configuration

— 48Kx24 Bit Y-Data RAM and 32Kx24 Bit Y-Data ROM

— 36Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM

— 64Kx24 Bit Program and Bootstrap ROM

— 4Kx24 Bit Program RAM.

— PROM patching mechanism

— Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to

Program RAM resulting in up to 44Kx24 Bit of Program RAM.

• Peripheral modules

— Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, left justified, right justified, Sony, AC97, network and other programmable protocols

— Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, left justified, right justified, Sony, AC97, network and other programmable protocols

— Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode, 10-word receive FIFO, support for 8, 16 and 24-bit words

— Triple Timer module (TEC).

— 11 dedicated GPIO pins

— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF,

IEC958, CP-340 and AES/EBU digital audio formats

— Pins of unused peripherals (except SHI) may be programmed as GPIO lines

Other data sheets within the file:

Datasheet

DSPD56371AF180 Datasheet

DSPD56371AF180 Datasheet

Application Notes

Application Optimization for the DSP56300/DSP56600 Digital Signal Processors

Application Optimization for the DSP56300/DSP56600 Digital Signal Processors

Characterizing CMOS DSP Core Current for Low-Power Applications

Characterizing CMOS DSP Core Current for Low-Power Applications

Considerations for Migrating Existing DSP563xx Designs to Symphony DSPs

Considerations for Migrating Existing DSP563xx Designs to Symphony DSPs

Designing Freescale DSP56xxx Software for Nonrealtime Tests File I/O Using SIM56xxx and ADS56xxx

Designing Freescale DSP56xxx Software for Nonrealtime Tests File I/O Using SIM56xxx and ADS56xxx

DSP56300 Assembly Code Development Using the Freescale Toolsets

DSP56300 Assembly Code Development Using the Freescale Toolsets


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