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Oct 19 2019

AT6003-2JC Datasheet PDF – IC FPGA 64 I/O 84PLCC Atmel

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-AT6003-2JC

Manufacturer Part#:

AT6003-2JC

Manufacturer

Atmel

Description:

IC FPGA 64 I/O 84PLCC

Package:

84-LCC (J-Lead)

Datasheet:

AT6003-2JC Datasheet

Stock:

Yes

Quantity:

91 PCS


AT6003-2JC Images are for reference only:

AT6003-2JC

 


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Atmel

Series

AT6000(LV)

Package/Case

84-LCC (J-Lead)

Clock Frequency-Max

250.0 MHz

Combinatorial Delay of a CLB-Max

2.4 ns

JESD-30 Code

S-PQCC-J84

JESD-609 Code

e0

Mounting Type

Surface Mount

Mounting Style

SMD/SMT

Moisture Sensitivity Level

2

Number of I/O

64

Number of Pins

84

Number of LABs/CLBs

1600

Number of Inputs

64.0

Number of Logic Elements Cells

1600.0

Number of Outputs

64.0

Number of Equivalent Gates

9000.0

Number of Terminals

84

Organization

1600 CLBS, 9000 GATES

Operating Temperature-Min

0.0°C

Operating Temperature-Max

70.0°C

Product Type

FPGA - Field Programmable Gate Array

Power Supplies

5

Packaging

Tube

Package Body Material

PLASTIC/EPOXY

Package Code

QCCJ

Package Equivalence Code

LDCC84,1.2SQ

Package Shape

SQUARE

Package Style

CHIP CARRIER

Peak Reflow Temperature

225°C

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Seated Height-Max

4.57 mm

Sub Category

Field Programmable Gate Arrays

Voltage-Supply

4.75 V ~ 5.25 V

Supply Voltage-Nom

5.0 V

Supply Voltage-Min

4.75 V

Supply Voltage-Max

5.25 V

Surface Mount

YES

Supplier Device Package

84-PLCC (29.31x29.31)

Technology

CMOS

Terminal Finish

Tin/Lead (Sn/Pb)

Terminal Form

J BEND

Terminal Pitch

1.27 mm

Terminal Position

QUAD

Temperature Grade

COMMERCIAL

Time@Peak Reflow Temperature-Max

30 s

Unit Weight

0.239083 oz

Length

29.3116 mm

Width

29.3116 mm

ECCN

3A991


AT6003-2JC Datasheet PDF Download: 

AT6003-2JC Datasheet PDF

Cell Structure

Cell Structure

Figure 1. Cell Structure

Cell-to-cell and Bus-to-bus Connections

Cell-to-cell and Bus-to-bus Connections

Figure 2. Cell-to-cell and Bus-to-bus Connections


Description

AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for use as reconfigurable coprocessors and implementing compute-intensive logic. Supporting system speeds greater than 100 MHz and using a typical operating current of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive designs. These FPGAs are designed to implement Cache Logic, which provides the user with the ability to implement adaptive hardware and perform hardware acceleration.

The patented AT6000 Series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O.

Features

• High-performance

– System Speeds > 100 MHz

– Flip-flop Toggle Rates > 250 MHz

– 1.2 ns/1.5 ns Input Delay

– 3.0 ns/6.0 ns Output Delay

• Up to 204 User I/Os

• Up to 6,400 Registers

• Cache Logic® Design

– Complete/Partial In-System Reconfiguration

– No Loss of Data or Machine State

– Adaptive Hardware

• Low Voltage and Standard Voltage Operation

– 5.0 (VCC = 4.75V to 5.25V)

– 3.3 (VCC = 3.0V to 3.6V)

• Automatic Component Generators

– Reusable Custom Hard Macro Functions

• Very Low-power Consumption

– Standby Current of 500 µA/ 200 µA

– Typical Operating Current of 15 to 170 mA

• Programmable Clock Options

– Independently Controlled Column Clocks

– Independently Controlled Column Resets

– Clock Skew Less Than 1 ns Across Chip

• Independently Configurable I/O (PCI Compatible)

– TTL/CMOS Input Thresholds

– Open Collector/Tristate Outputs

– Programmable Slew-rate Control

– I/O Drive of 16 mA (combinable to 64 mA)


Other data sheets within the file:

Datasheet

AT6003-2JC Datasheet

AT6003-2JC Datasheet


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