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Mar 28 2019

APA150-TQG100I Datasheet PDF - 0.50 MM PITCH, ROHS COMPLIANT, TQFP-100

Product Overview

Product Category:Embedded - FPGAs (Field Programmable Gate Array)
Kynix Part #:KY32-APA150-TQG100I
Manufacturer Part#:APA150-TQG100I
Manufacturer:Microsemi Corporation
Description:FPGA ProASICPLUS Family 150K Gates 180MHz 0.22um Technology 2.5V 100-Pin TQFP Tray
Package:QFP
Datasheet:APA150-TQG100I Datasheet
Stock:Yes
Quantity:780PCS

APA150-TQG100I Images are for reference only:

fpga  APA150-TQG100I.jpg

APA150-TQG100I.jpg

Product Specifications

Product CategoryFPGA - Field Programmable Gate Array
Shipping Restrictions This product may require additional documentation to export from the United States.
Package Description 0.50 MM PITCH, ROHS COMPLIANT, TQFP-100
Number of I/Os   66
Operating Supply Voltage (V)2.5
Mounting Style  SMD/SMT
Package / Case   TQFP-100
Package ShapeSQUARE
Package StyleFLATPACK, LOW PROFILE, FINE PITCH
Packaging Tray
Height (mm)1.4
Length (mm)14
Series  ProASICPLUS
Width (mm)14
Brand  Microsemi 
Maximum Operating Frequency (MHz)    180
Factory Pack Quantity  90
Subcategory    Programmable Logic ICs
Supply Voltage - Max (V)2.7
Supply Voltage - Min (V)2.3
Tradename    Actel
Unit Weight  0.023175oz
Total RAM (bit) 36864
Number of Gates150000
Mounting Surface Mount
Operating Temperature-40°C ~ 85°C (TA)
Package / Case100-LQFP
Supplier Device Package100-TQFP (14x14)
Base Part NumberAPA150
Environmental & Export  Classifications
Lead Free Status / RoHS Status Compliant
Moisture Sensitivity Level (MSL)3 (168 Hours)
ECCN (US)3A001.a.7.a
Part Status  Active
HTS   8542.39.00.01
Clock Frequency-Max (MHz)180
JESD-30 CodeS-PQFP-G100
JESD-609 Codee3
Process Technology (um)0.22
Number of Inter Dielectric Layers4
Number of Registers  6144
Program Memory Type   Flash
Embedded Memory (Kbit)   36
Total Number of Block RAM   16
Device System Gates  150000
Number of Global Clocks  4
Device Number of DLLs/PLLs   2
PCIe1
Programmability   Yes
Reprogrammability Support  Yes
Copy Protection   No
In-System Programmability  Yes
Speed Grade  STD
I/O Voltage (V)   3.3|2.5
Supplier Temperature Grade  Industrial
TradenamePro   ASIC
Supplier Package  TQFP
Standard Package Name  QFP
Pin Count   100
PCB changed   100
Lead Shape  Gull-wing
TechnologyCMOS
Temperature Grade INDUSTRIAL
Terminal FinishMATTE TIN
Terminal FormGULL WING
Terminal Pitch(mm)  0.5
Terminal PositionQUAD



APA150-TQG100I Datasheet PDF Download:

APA150-TQG100I Datasheet PDF

Pin Description

User Pins

I/O User     Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors.

NC       No Connect
To maintain compatibility with other Actel ProASICPLUS products, it is recommended that this pin not be connected to the circuitry on the board.
GL    Global Pin
Low skew input pin for clock or other global signals. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal I/O.
GLMX Global    Multiplexing Pin
Low skew input pin for clock or other global signals. This pin can be used in one of two special ways (refer to Actel’s Using

ProASIC PLUS Clock Conditioning Circuits). 

When the external feedback option is selected for the PLL block, this pin is routed as the external feedback source to the clock conditioning circuit.
In applications where two different signals access the same global net at different times through the use of GLMXx and GLMXLx macros, this pin will be fixed as one of the source pins.
This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal I/O. If not used, the GLMXx pin will be configured as an input with pull-up.

Dedicated Pins

GND    Ground
Common ground supply voltage.

VDD    

Logic Array Power Supply Pin
2.5 V supply voltage.

VDDP   

I/O Pad Power Supply Pin
2.5 V or 3.3 V supply voltage.
TMS   Test Mode Select
The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor.
TCK   Test Clock
Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20 kΩ pull-up resistor to this pin.
TDI   Test Data In
Serial input for boundary scan. A dedicated pull-up resistor is included to pull this pin high when not being driven.
TDO   Test Data Out
Serial output for boundary scan. Actel recommends adding a nominal 20kΩ pull-up resistor to this pin.
TRST   Test Reset Input
Asynchronous, active low input pin for resetting boundary-scan circuitry. This pin has an internal pull-up resistor. For more information, please refer to Power-up Behavior of ProASIC PLUS Devices application note.

Special Function Pins

RCK    Running Clock
A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. If not used, this pin has an internal pullup and can be left floating.
NPECL    User Negative Input
Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected.
PPECL   User Positive Input
Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected.
AVDD     PLL Power Supply
Analog VDD should be VDD (core voltage) 2.5 V (nominal) and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel’s Using ProASIC PLUS Clock Conditioning Circuits application note. If the clock conditioning circuitry is not used in a design, AVDD can either be left floating or tied to 2.5 V.
AGND      PLL Power Ground
The analog ground can be connected to the system ground. For more information, refer to Actel’s Using ProASIC PLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AGND should be tied to GND.


Package Pin Assignments

100-Pin TQFP.jpg

Fig. 1 100-Pin TQFP

144-Pin FBGA.jpg

Fig. 2 144-Pin FBGA

144-Pin TQFP.jpg

Fig. 3 144-Pin TQFP

208-Pin CQFP.jpg

Fig. 4 208-Pin CQFP

208-Pin PQFP.jpg

Fig. 5 208-Pin PQFP

256-Pin FBGA.jpg

Fig. 6 256-Pin FBGA

352-Pin CQFP.jpg

Fig. 7 352-Pin CQFP

456-Pin PBGA.jpg

Fig. 8 456-Pin PBGA

484-Pin FBGA

Fig. 9 484-Pin FBGA

624-Pin CCGA LGA

Fig. 10 624-Pin CCGA LGA

676-Pin FBGA

Fig. 11 676-Pin FBGA

896-Pin FBGA

Fig. 12 896-Pin FBGA

1152-Pin FBGA

Fig. 13 1152-Pin FBGA

Features and Benefits

High Capacity

Commercial and Industrial

• 75,000 to 1 Million System Gates

• 27 K to 198 Kbits of Two-Port SRAM

• 66 to 712 User I/Os

Military

• 300, 000 to 1 Million System Gates

• 72 K to 198 Kbits of Two Port SRAM

• 158 to 712 User I/Os

Reprogrammable Flash Technology

• 0.22 µm 4 LM Flash-Based CMOS Process

• Live At Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• No Configuration Device Required

• Retains Programmed Design during Power-Down/Up Cycles

• Mil/Aero Devices Operate over Full Military Temperature Range

Performance

• 3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military

temperature)

• Two Integrated PLLs

• External System Performance up to 150 MHz

Secure Programming

• The Industry’s Most Effective Security Key (FlashLock®)

Low Power

• Low Impedance Flash Switches

• Segmented Hierarchical Routing Structure

• Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells

High Performance Routing Hierarchy

• Ultra-Fast Local and Long-Line Network

• High-Speed Very Long-Line Network

• High-Performance, Low Skew, Splittable Global Network

• 100% Routability and Utilization

I/O

• Schmitt-Trigger Option on Every Input

• 2.5 V / 3.3 V Support with Individually-Selectable Voltage and Slew Rate

• Bidirectional Global I/Os

• Compliance with PCI Specification Revision 2.2

• Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant

• Pin-Compatible Packages across the ProASICPLUS Family

Unique Clock Conditioning Circuitry

• PLL with Flexible Phase, Multiply/Divide, and Delay

Capabilities

• Internal and/or External Dynamic PLL Configuration

• Two LVPECL Differential Pairs for Clock or Data Inputs

Standard FPGA and ASIC Design Flow

• Flexibility with Choice of Industry-Standard Front-End Tools

• Efficient Design through Front-End Timing and Gate Optimization

ISP Support

• In-System Programming (ISP) via JTAG Port

SRAMs and FIFOs

• SmartGen Netlist Generation Ensures Optimal Usage of

Embedded Memory Blocks

• 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical)

Other data sheets within the file:

APA150-TQG100I DatasheetAPA150-TQG100I Datasheet
Actel - PCN - 7-28-10Actel - PCN - 7-28-10 PDF
Actel - PCN 5-18-10Actel - PCN 5-18-10 PDF
Product Change NotificationProduct Change Notification PDF
Product Change NotificationProduct Change Notification PDF

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