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Nov 16 2019

ADSP-TS202SABPZ050 Datasheet PDF – IC PROCESSOR 500MHZ 576BGA AD

Product Overview

Product Category:

Embedded - DSP (Digital Signal Processors)

Kynix Part #:

KY32- ADSP-TS202SABPZ050

Manufacturer Part#:

ADSP-TS202SABPZ050

Manufacturer

AD

Description:

IC PROCESSOR 500MHZ 576BGA

Package:

BGA

Datasheet:

ADSP-TS202SABPZ050 Datasheet

Stock:

Yes

Quantity:

72 PCS


ADSP-TS202SABPZ050 Images are for reference only:

ADSP-TS202SABPZ050

 


Product Specifications

Product Category

Embedded - DSP (Digital Signal Processors)

Manufacturer

AD

Series

TigerSHARC®

Packaging

Tray

Package/Case

575-BBGA

Address Bus Width

32.0

Barrel Shifter

Yes

Boundary Scan

Yes

Clock Rate

500 MHz

Clock Frequency-Max

125.0 MHz

Data Bus Width

32 bit

Data RAM Size

1.5 MB

ECCN (US)

3A991.a.2

EU RoHS Compliant

Yes

External Data Bus Width

64.0

Format

FLOATING POINT

Frequency

500 MHz

Interface

Host Interface, Link Port, Multi-Processor

Internal Bus Architecture

MULTIPLE

JESD-30 Code

S-PBGA-B576

JESD-609 Code

e1

Low Power Mode

No

Memory Size

12 MB

Mounting Type

Surface Mount

Mounting Style

SMD/SMT

Moisture Sensitivity Level

3

Maximum Clock Frequency

500 MHz

Number of Pins

576

Number of Terminals

576

Number of Timers/Counters

2

Non-Volatile Memory

External

On-Chip RAM

1.5MB

Operating Temperature-Min

-40.0 °C

Operating Temperature-Max

85.0°C

Package Body Material

PLASTIC/EPOXY

Package Code

BGA

Package Shape

SQUARE

Package Style

GRID ARRAY

Product Type

DSP - Digital Signal Processors & Controllers

Peak Reflow Temperature

260 °C

Program Memory Size

12 MB

RAM Size

1.5 MB

Seated Height-Max

3.1 mm

Supply Voltage-Nom

1.05 V

Supply Voltage-Min

1.0 V

Supply Voltage-Max

1.1 V

Surface Mount

Yes

Supplier Device Package

576-BGA-ED (25x25)

Technology

CMOS

Terminal Form

BALL

Terminal Pitch

1.0 mm

Terminal Finish

TIN SILVER COPPER

Terminal Position

BOTTOM

Temperature Grade

INDUSTRIAL

Time@Peak Reflow Temperature-Max

40 s

Voltage - I/O

2.50 V

Voltage - Core

1.05 V

Length

25.0 mm

Width

25.0 mm


ADSP-TS202SABPZ050 Datasheet PDF Download:
 

ADSP-TS202SABPZ050 Datasheet PDF 

Functional Block Diagram

 Figure 1. Functional Block Diagram

Figure 1. Functional Block Diagram

ADSP-TS202S Memory Map

Figure 2. ADSP-TS202S Memory Map 

Figure 2. ADSP-TS202S Memory Map

Description

The ADSP-TS202S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP

combines very wide memory widths with dual computation blocks—supporting floating-point (IEEE 32-bit and extended precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) processing—to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

Four independent 128-bit wide internal data buses, each connecting to the six 2M bit memory banks, enable quad-word data, instruction, and I/O accesses and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS202S processor’s core has a 2.0 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS202S processor can perform four billion 40-bit MACS or one billion 80-bit MACS per second.

Features

• 500 MHz, 2.0 ns instruction cycle rate

• 12M bits of internal—on-chip—DRAM memory 

• 25 mm × 25 mm (576-ball) thermally enhanced ball grid array package

• Dual-computation blocks—each containing an ALU, a multiplier, a shifter, and a register file

• Dual-integer ALUs, providing data addressing and pointer manipulation

• Single-precision IEEE 32-bit and extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats

• Integrated I/O includes 14-channel DMA controller, external port, four link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration

• 1149.1 IEEE-compliant JTAG test access port for on-chip emulation

• On-chip arbitration for glueless multiprocessing


Other data sheets within the file:

Datasheet

ADSP-TS202SABPZ050 Datasheet

ADSP-TS202SABPZ050 Datasheet

PCN Obsolescence/ EOL

EOL 24/Mar/2016

EOL 24/Mar/2016


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