Product Overview
Product Category: | Embedded - DSP (Digital Signal Processors) |
Kynix Part #: | KY32- ADSP-21161NKCA-100 |
Manufacturer Part#: | ADSP-21161NKCA-100 |
Manufacturer | Analog Devices Inc. |
Description: | IC DSP CONTROLLER 32BIT 225MBGA |
Package: | 225-BGA, CSPBGA |
Datasheet: | |
Stock: | Yes |
Quantity: | 126 PCS |
ADSP-21161NKCA-100 Images are for reference only:
Product Specifications
Product Category | Embedded - DSP (Digital Signal Processors) |
Manufacturer | Analog Devices Inc. |
Series | SHARC® |
Packaging | Tray |
Package-Case | 225-BGA, CSPBGA |
Address Bus Width | 24.0 |
Bit Size | 32 |
Barrel Shifter | Yes |
Boundary Scan | Yes |
Clock Rate | 100 MHz |
Clock Frequency-Max | 27.5 MHz |
Data Bus Width | 32 bit |
Device Input Clock Speed | 100 MHz |
ECCN (US) | 3A991.a.2 |
Ethernet | 0 |
External Data Bus Width | 48.0 |
Format | FLOATING POINT |
Family Name | ADSP-2116x |
HTS | 8542.31.00.01 |
Interface | Host Interface, Link Port, Serial Port |
Interface Type | SPI |
Internal Bus Architecture | MULTIPLE |
Instruction Set Architecture | Enhanced Harvard |
JESD-30 Code | S-PBGA-B225 |
JESD-609 Code | e0 |
Lead Shape | Ball |
Low Power Mode | No |
Mounting Type | Surface Mount |
Moisture Sensitivity Level | 3 |
Minimum Operating Supply Voltage (V) | 1.71|3.13 |
Maximum Operating Supply Voltage (V) | 1.89|3.47 |
Microprocessor/Microcontroller/Peripheral IC Type | DIGITAL SIGNAL PROCESSOR, OTHER |
Non-Volatile Memory | External |
Number of Terminals | 225 |
Numeric and Arithmetic Format | Floating-Point |
On-Chip RAM | 128 kB |
Operating Temperature-Min | 0.0 °C |
Operating Temperature-Max | 85.0°C |
Pin Count | 225 |
Package Body Material | PLASTIC/EPOXY |
Package Code | BGA |
Package Equivalence Code | BGA225,15X15,40 |
Package Shape | SQUARE |
Package Style | GRID ARRAY |
Package Height | 1.1(Max) |
Package Length | 17 |
Package Width | 17 |
PCB changed | 225 |
Peak Reflow Temperature | NOT SPECIFIED |
Power Supplies | 1.8,3.3 |
Program Memory Type | ROMLess |
Programmability | No |
RAM Size | 128 KB |
RAM (words) | 32768 |
Rad Hardened | No |
REACH Compliant | Yes |
Seated Height-Max | 1.85 mm |
Sub Category | Digital Signal Processors |
Supplier Package | CSP-BGA |
Supply Voltage-Nom | 1.8 V |
Supply Voltage-Min | 1.71 V |
Supply Voltage-Max | 1.89 V |
Surface Mount | Yes |
Standard Package Name | BGA |
Supplier Device Package | 225-CSPBGA (17x17) |
Type | Floating Point |
Technology | CMOS |
Terminal Finish | Tin/Lead/Silver (Sn/Pb/Ag) |
Terminal Form | BALL |
Terminal Pitch | 1.0 mm |
Terminal Position | BOTTOM |
Temperature Grade | OTHER |
Typical Operating Supply Voltage (V) | 3.3|1.8 |
Time@Peak Reflow Temperature-Max | NOT SPECIFIED |
Voltage - I/O | 3.30 V |
Voltage - Core | 1.80 V |
Length | 17.0 mm |
Width | 17.0 mm |
SPI | 1 |
I2S | 0 |
I2C | 0 |
CAN | 0 |
USB | 0 |
UART | 0 |
USART | 0 |
ADSP-21161NKCA-100 Datasheet PDF Download:
Block Diagram
ADSP-21161N Functional Block Diagram
System Diagram
System Diagram
Memory Map
Memory Map
Description
The ADSP-21161N SHARC® DSP is a low cost derivative of the ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161N is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the ADSP21161N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21161N includes a 100 MHz or 110 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.
As was first offered in the ADSP-21160, the ADSP-21161N offers a single-instruction multiple-data (SIMD) architecture. Using two computational units (ADSP-2106x SHARC processors have one), the ADSP-21161N can double cycle performance versus the ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21161N has a 10 ns or 9 ns instruction cycle time. With its SIMD computational hardware running at 110 MHz, the ADSP-21161N can perform 660 million floatingpoint operations per second.
These benchmarks provide single-channel extrapolations of measured dual-channel processing performance.
Features
• Two processing elements, each made up of an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle
• Interval timer
• On-Chip SRAM (1M bit)
• SDRAM controller for glueless interface to SDRAMs
• External port that supports:
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six ADSP-21161N SHARCs
• Host port read/write of IOP registers
• DMA controller
• Four serial ports
• Two link ports
• SPI compatible interface
• JTAG test access port
• 12 general-purpose I/O pins
Other data sheets within the file:
Datasheet | |
ADSP-21161NKCA-100 Datasheet | ![]() |