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Oct 19 2019

A40MX04-PLG68 Datasheet PDF – IC FPGA 57 I/O 68PLCC Microsemi Corporation

Product Overview

Product Category:

Embedded - FPGAs (Field Programmable Gate Array)

Kynix Part #:

KY32-A40MX04-PLG68

Manufacturer Part#:

A40MX04-PLG68

Manufacturer

Microsemi Corporation

Description:

IC FPGA 57 I/O 68PLCC

Package:

68-LCC (J-Lead)

Datasheet:

A40MX04-PLG68 Datasheet

Stock:

Yes

Quantity:

124 PCS


A40MX04-PLG68 Images are for reference only:

 A40MX04-PLG68


Product Specifications

Product Category

Embedded - FPGAs (Field Programmable Gate Array)

Manufacturer

Microsemi Corporation

Status

Active

Series

MX

Packaging

Tray

Package-Case

68-LCC (J-Lead)

Clock Frequency-Max

80.4 MHz

Combinatorial Delay of a CLB-Max

2.7 ns

Copy Protection

No

EU RoHS Compliant

Yes

Device Logic Units

547

Device Logic Gates

6000

Device System Gates

6000

In-System Programmability

No

JESD-30 Code

S-PQCC-J68

JESD-609 Code

e3

Mounting-Style

SMD/SMT

Mounting-Type

Surface Mount

Moisture Sensitivity Level

3

Maximum-Operating-Frequency

139 MHz

Number of I/O

57

Number of Inputs

69.0

Number of Logic Cells

547.0

Number of Outputs

69.0

Number of Pins

68

Number of Terminals

68

Number of Registers

273

Number of Global Clocks

1

Number of Equivalent Gates

6000.0

Number of Inter Dielectric Layers

3

Number of Logic Elements/Cells

547

Organization

547 CLBS, 6000 GATES

Operating Temperature-Min

0.0°C

Operating Temperature-Max

70.0°C

Pin Count

68

Power Supplies

3.3/5

Package Body Material

PLASTIC/EPOXY

Package Code

QCCJ

Package Equivalence Code

LDCC68,1.0SQ

Package Shape

SQUARE

Package Style

CHIP CARRIER

Peak Reflow Temperature

245°C

Programmable Logic Type

FIELD PROGRAMMABLE GATE ARRAY

Programmability

Yes

Process Technology

0.45 um

REACH Compliant

Yes

Speed Grade

STD

Reprogrammability Support

No

Supplier Temperature Grade

Commercial

Seated Height-Max

4.57 mm

Sub Category

Field Programmable Gate Arrays

Voltage-Supply

3.0 V ~ 3.6 V

Supply Voltage-Nom

3.3 V

Supply Voltage-Min

3.0 V

Supply Voltage-Max

3.6 V

Surface Mount

Yes

Technology

CMOS

Terminal Finish

MATTE TIN

Terminal Form

J BEND

Terminal Pitch

1.27 mm

Terminal Position

QUAD

Temperature Grade

COMMERCIAL

Tradename

Actel

Time@Peak Reflow Temperature-Max

40 s

Length

24.2316 mm

Width

24.2316 mm


A40MX04-PLG68 Datasheet PDF Download: 

A40MX04-PLG68 Datasheet PDF

Ordering Information

Figure 1. Ordering Information

Figure 1. Ordering Information


Description

Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost

■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and 0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power consumption, Cyclone III device family makes it easier for you to meet your power budget. Cyclone III LS devices are the first to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power and high-functionality FPGA platform. This suite of security features protects the IP from tampering, reverse engineering and cloning. In addition, Cyclone III LS devices support design separation which enables you to introduce redundancy in a single chip to reduce size, weight, and power of your application.

Features

High Capacity

• Single-Chip ASIC Alternative

• 3,000 to 54,000 System Gates

• Up to 2.5 kbits Configurable Dual-Port SRAM

• Fast Wide-Decode Circuitry

• Up to 202 User-Programmable I/O Pins

High Performance

• 5.6 ns Clock-to-Out

• 250 MHz Performance

• 5 ns Dual-Port SRAM Access

• 100 MHz FIFOs

• 7.5 ns 35-Bit Address Decode

HiRel Features

• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages

• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages

• QML Certification

• Ceramic Devices Available to DSCC SMD

Ease of Integration

• Mixed-Voltage Operation (5.0 V or 3.3 V for core and I/Os), with PCI-Compliant I/Os

• Up to 100% Resource Utilization and 100% Pin Locking

• Deterministic, User-Controllable Timing

• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II

• Low Power Consumption

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing


Other data sheets within the file:

Datasheet

A40MX04-PLG68 Datasheet

A40MX04-PLG68 Datasheet


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